Patents by Inventor Simon Ruffell

Simon Ruffell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200194271
    Abstract: A method of patterning a substrate. The method may include providing a cavity in a layer, disposed on the substrate, the cavity having a first length along a first direction and a first width along a second direction, perpendicular to the first direction, and wherein the layer has a first height along a third direction, perpendicular to the first direction and the second direction. The method may include depositing a sacrificial layer over the cavity in a first deposition procedure; and directing angled ions to the cavity in a first exposure, wherein the cavity is etched, and wherein after the first exposure, the cavity has a second length along the first direction, greater than the first length, and wherein the cavity has a second width along the second direction, no greater than the first width.
    Type: Application
    Filed: November 7, 2019
    Publication date: June 18, 2020
    Applicant: APPLIED Materials, Inc.
    Inventors: Kevin Anglin, Simon Ruffell
  • Patent number: 10665421
    Abstract: A system for determining various parameters of an ion beam is disclosed. A test workpiece may be modified to incorporate a detection pattern. The detection pattern may be configured to measure the height of the ion beam, the uniformity of the ion beam, or the central angle of the ion beam. In certain embodiments, the amount of current striking the detection pattern may be measured using an optical emission spectrometer (OES) system. In other embodiments, a power supply used to bias the workpiece may be used to measure the amount of current striking the detection pattern. Alternative, the detection patterns may be incorporated into the workpiece holder.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: May 26, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Tsung-Liang Chen, Kevin R. Anglin, Simon Ruffell
  • Publication number: 20200118790
    Abstract: A system for determining various parameters of an ion beam is disclosed. A test workpiece may be modified to incorporate a detection pattern. The detection pattern may be configured to measure the height of the ion beam, the uniformity of the ion beam, or the central angle of the ion beam. In certain embodiments, the amount of current striking the detection pattern may be measured using an optical emission spectrometer (OES) system. In other embodiments, a power supply used to bias the workpiece may be used to measure the amount of current striking the detection pattern. Alternative, the detection patterns may be incorporated into the workpiece holder.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventors: Tsung-Liang Chen, Kevin R. Anglin, Simon Ruffell
  • Publication number: 20200090909
    Abstract: A method may include providing a cavity in a surface of a substrate, the cavity comprising a sidewall portion and a lower surface; directing depositing species to the surface of the substrate, wherein the depositing species condense to form a fill material on the sidewall portion and lower surface; and directing angled ions at the cavity at a non-zero angle of incidence with respect to a perpendicular to a plane defined by the substrate, wherein the angled ions strike an exposed part of the sidewall portion and do not strike the lower surface, and wherein the cavity is filled by the fill material in a bottom-up fill process.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala
  • Patent number: 10546730
    Abstract: A method may include providing a cavity in a surface of a substrate, the cavity comprising a sidewall portion and a lower surface; directing depositing species to the surface of the substrate, wherein the depositing species condense to form a fill material on the sidewall portion and lower surface; and directing angled ions at the cavity at a non-zero angle of incidence with respect to a perpendicular to a plane defined by the substrate, wherein the angled ions strike an exposed part of the sidewall portion and do not strike the lower surface, and wherein the cavity is filled by the fill material in a bottom-up fill process.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 28, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC
    Inventors: Simon Ruffell, John Hautala
  • Publication number: 20190355581
    Abstract: A method of patterning a substrate may include providing a cavity in a layer, disposed on the substrate. The cavity may have a first length along a first direction and a first width along a second direction, perpendicular to the first direction. The method may include directing first angled ions in a first exposure to the cavity, wherein after the first exposure the cavity has a second length, greater than the first length; directing normal ions in a second exposure to the cavity, wherein the cavity retains the second length after the second exposure; and directing second angled ions to the cavity is a third exposure, subsequent to the second exposure, wherein the cavity has a third length, greater than the second length, after the third exposure.
    Type: Application
    Filed: August 2, 2018
    Publication date: November 21, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin R. Anglin, Simon Ruffell
  • Publication number: 20190272983
    Abstract: A substrate assembly may include an outer halo, the outer halo comprising a first material and defining a first aperture. The substrate assembly may also include a halo ring, comprising a second material and disposed at least partially within the first aperture. The halo ring may define a second aperture, concentrically positioned within the first aperture, wherein the halo ring is coupled to accommodate a substrate therein.
    Type: Application
    Filed: May 2, 2018
    Publication date: September 5, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jay Wallace, Simon Ruffell, Kevin Anglin, Tyler Rockwell, Chris Campbell, Kevin M. Daniels, Richard J. Hertel
  • Patent number: 10381232
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 13, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
  • Patent number: 10280512
    Abstract: In one embodiment, an apparatus to selectively deposit a carbon layer on substrate, comprising a plasma chamber to receive a flow of carbon-containing gas; a power source to generate a plasma containing the carbon-containing gas in the plasma chamber; an extraction plate to extract an ion beam from the plasma and direct the ion beam to the substrate, the ion beam comprising ions having trajectories forming a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, the extraction plate further configured to conduct a neutral species derived from the carbon-containing gas to the substrate; and a substrate stage facing the extraction plate and including a heater to heat the substrate to a first temperature, when the ion beam and carbon-containing species impinge on the substrate.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 7, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Alex Tsung-Liang Chen, Simon Ruffell
  • Patent number: 10229832
    Abstract: A method of patterning a substrate. The method may include: providing a first surface feature and a second surface feature in a staggered configuration within a layer, the layer being disposed on the substrate, and directing first ions in a first exposure to a first side of the first surface feature and a first side of the second surface feature, in a presence of a reactive ambient containing a reactive species, wherein the first exposure etches the first side of the first surface feature and the first side of the second surface feature, wherein after the directing, the first surface feature and the second surface feature merge to form a third surface feature.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: March 12, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Steven R. Sherman, John Hautala, Simon Ruffell
  • Patent number: 10222202
    Abstract: An apparatus may include a processor and memory unit, including a control routine having a measurement processor to determine, based upon a first set of scatterometry measurements, a first change in a first dimension of a first set of substrate features along a first direction. The first set of substrate features may be elongated along a second direction perpendicular to the first direction. The measurement processor may be to determine, based upon a second set of scatterometry measurements, a second change in dimension of a second set of substrate features along the second direction, wherein the second set of substrate features is elongated along the first direction. The apparatus may include a control processor to generate an error signal when a figure of merit based upon the first change and the second change lies outside a target range.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: March 5, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Morgan D. Evans, Simon Ruffell, Tristan Y. Ma, Kevin Anglin
  • Patent number: 10204909
    Abstract: Provided herein are approaches for forming a gate oxide layer for a DRAM device, the method including providing a finned substrate having a recess formed therein, and performing an ion implant into a sidewall surface of the recess to form a gate oxide layer having a non-uniform thickness, wherein a thickness of the gate oxide layer at a top section of the sidewall surface is greater than a thickness of the gate oxide layer at a bottom section of the sidewall surface. In some approaches, the ion implant is provided as a series of ion implants at multiple different implant angles, varied along with an ion implantation energy and/or an ion dose to increase the thickness of the gate oxide of the top section of the sidewall surface. In some approaches, the finned substrate is also exposed to a plasma, either during or after, the ion implantation.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 12, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, Arvind Kumar, Tristan Ma, Kyu-Ha Shim, John Hautala, Steven Sherman
  • Publication number: 20180340769
    Abstract: An apparatus may include a processor and memory unit, including a control routine having a measurement processor to determine, based upon a first set of scatterometry measurements, a first change in a first dimension of a first set of substrate features along a first direction. The first set of substrate features may be elongated along a second direction perpendicular to the first direction. The measurement processor may be to determine, based upon a second set of scatterometry measurements, a second change in dimension of a second set of substrate features along the second direction, wherein the second set of substrate features is elongated along the first direction. The apparatus may include a control processor to generate an error signal when a figure of merit based upon the first change and the second change lies outside a target range.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Simon Ruffell, Tristan Y. MA, Kevin Anglin
  • Publication number: 20180330944
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 15, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Patent number: 10109494
    Abstract: A method may include providing a patterned feature extending from a substrate plane of a substrate, the patterned feature including a semiconductor portion and a coating in an unhardened state extending along a top region and along sidewall regions of the semiconductor portion; implanting first ions into the coating, the first ions having a first trajectory along a perpendicular to the substrate plane, wherein the first ions form a etch-hardened portion comprising a hardened state disposed along the top region; and directing a reactive etch using second ions at the coating, the second ions having a second trajectory forming a non-zero angle with respect to the perpendicular, wherein the reactive etch removes the etch-hardened portion at a first etch rate, wherein the first etch rate is less than a second etch rate when the second ions are directed in the reactive etch to the top portion in the unhardened state.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 23, 2018
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventor: Simon Ruffell
  • Publication number: 20180261463
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Application
    Filed: May 11, 2018
    Publication date: September 13, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
  • Publication number: 20180182637
    Abstract: A method of treating a substrate includes directing ions to the substrate along at least one non-zero angle with respect to a perpendicular to a substrate surface in a presence of a reactive ambient containing a reactive species where the substrate includes a surface feature. At least one surface of the surface feature is etched using the ions in combination with the reactive ambient at a first etch rate that is greater than a second etch rate when the ions are directed to the substrate without the reactive ambient and greater than a third etch rate when the reactive ambient is provided to the substrate without the ions.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Steven R. Sherman, Simon Ruffell, John Hautala, Adam Brand
  • Patent number: 10008384
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 26, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Patent number: 9984889
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 29, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
  • Patent number: 9934981
    Abstract: A method of treating a substrate includes directing ions to the substrate along at least one non-zero angle with respect to a perpendicular to a substrate surface in a presence of a reactive ambient containing a reactive species where the substrate includes a surface feature. At least one surface of the surface feature is etched using the ions in combination with the reactive ambient at a first etch rate that is greater than a second etch rate when the ions are directed to the substrate without the reactive ambient and greater than a third etch rate when the reactive ambient is provided to the substrate without the ions.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 3, 2018
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Steven R. Sherman, Simon Ruffell, John Hautala, Adam Brand