Patents by Inventor Simon Siu-Sing Chan
Simon Siu-Sing Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11183509Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: GrantFiled: June 18, 2020Date of Patent: November 23, 2021Assignee: Cypress Semiconductor CorporationInventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Publication number: 20200411537Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: ApplicationFiled: June 18, 2020Publication date: December 31, 2020Applicant: Infineon Technologies LLCInventors: Ching-Huang LU, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Patent number: 10256137Abstract: An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: GrantFiled: November 3, 2017Date of Patent: April 9, 2019Assignee: Cypress Semiconductor CorporationInventors: Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
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Publication number: 20180166323Abstract: A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the buried trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: ApplicationFiled: November 3, 2017Publication date: June 14, 2018Applicant: Cypress Semiconductor CorporationInventors: Ching-Huang LU, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
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Patent number: 9831114Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: GrantFiled: June 24, 2016Date of Patent: November 28, 2017Assignee: Cypress Semiconductor CorporationInventors: Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Rinji Sugino, Simon Siu-Sing Chan
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Patent number: 9666591Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: GrantFiled: January 26, 2016Date of Patent: May 30, 2017Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Patent number: 9437470Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: GrantFiled: October 8, 2013Date of Patent: September 6, 2016Assignee: Cypress Semiconductor CorporationInventors: Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
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Publication number: 20160211271Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: ApplicationFiled: January 26, 2016Publication date: July 21, 2016Inventors: Ching-Huang LU, Simon Siu-Sing CHAN, Hidehiko Shiraiwa, Lei Xue
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Publication number: 20160211321Abstract: A system for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) is disclosed herein. An integrated circuit (IC) comprises a substrate, a first device, a second device, and an isolator. The isolator is positioned between first and second device. The isolator comprises one or more cavities. The isolator may be filled with dielectric material.Type: ApplicationFiled: February 1, 2016Publication date: July 21, 2016Inventors: Rinji Sugino, Lei Xue, Ching-Huang LU, Simon Siu-Sing CHAN
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Patent number: 9252154Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: GrantFiled: September 30, 2014Date of Patent: February 2, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Publication number: 20150097224Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is positioned between first and second devices and comprises a first filled portion and a second filled portion. The first filled portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: Spansion LLCInventors: Lei XUE, Ching-Huang LU, Simon Siu-Sing CHAN
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Publication number: 20150097245Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: Spansion LLCInventors: Ching-Huang LU, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
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Publication number: 20150017795Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Patent number: 8866213Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: GrantFiled: January 30, 2013Date of Patent: October 21, 2014Assignee: Spansion LLCInventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Publication number: 20140209993Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: Spansion LLCInventors: Ching-Huang LU, Simon Siu-Sing CHAN, Hidehiko SHIRAIWA, Lei XUE
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Patent number: 8598005Abstract: A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.Type: GrantFiled: July 18, 2011Date of Patent: December 3, 2013Assignee: Spansion LLCInventors: Simon Siu-Sing Chan, Hidehiko Shiraiwa, Chuan Lin, Lei Xue, Kenichi Ohtsuka, Angela Tai Hui
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Publication number: 20130023101Abstract: A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.Type: ApplicationFiled: July 18, 2011Publication date: January 24, 2013Applicant: Spansion LLCInventors: Simon Siu-Sing Chan, Hidehiko Shiraiwa, Chuan Lin, Lei Xue, Kenichi Ohtsuka, Angela Tai Hui
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Patent number: 8114736Abstract: A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.Type: GrantFiled: December 17, 2007Date of Patent: February 14, 2012Assignees: Globalfoundries Inc., Spansion LLCInventors: Simon Siu-Sing Chan, Hidehiko Shiraiwa, Kuo-Tung Chang, Angela T. Hui
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Patent number: 8102009Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.Type: GrantFiled: October 3, 2006Date of Patent: January 24, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Simon Siu-Sing Chan, Paul R. Besser, Jeffrey P. Patton
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Patent number: 7843015Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.Type: GrantFiled: September 15, 2005Date of Patent: November 30, 2010Assignee: GLOBALFOUNDRIES Inc.Inventors: Robert J. Chiu, Paul R. Besser, Simon Siu-Sing Chan, Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Errol Todd Ryan