Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

Abstract: An integrated electronic circuit including: a dielectric body delimited by a front surface; A top conductive region of an integrated electronic circuit extend within a dielectric body having a front surface. A passivation structure including a bottom portion and a top portion laterally delimits an opening. The bottom portion extends on the front surface, and the top portion extends on the bottom portion. A field plate includes an internal portion and an external portion. The internal portion is located within the opening and extends on the top portion of the passivation structure. The external portion extends laterally with respect to the top portion of the passivation structure and contacts at a bottom one of: the dielectric body or the bottom portion of the passivation structure. The opening and the external portion are arranged on opposite sides of the top portion of the passivation structure.

Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

Abstract: An integrated device includes a deep plug. The deep plug is formed by a deep trench extending in a semiconductor body from a shallow surface of a shallow trench isolation. A trench contact makes contact with a conductive filler of the deep trench through the shallow trench at its shallow surface. A system includes at least one integrated device with the deep plug. Moreover, a corresponding process for manufacturing this integrated device includes steps for forming and filling the deep trench before forming the shallow trench isolation and trench window through which the trench contact extends to make contact with the conductive filler. The semiconductor body has a thickness, and the deep trench extends into the semiconductor body less than the thickness.

Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

Abstract: A vertical-conduction semiconductor electronic device includes: a semiconductor body; a body region in the semiconductor body; a source terminal in the body region; a drain terminal spatially opposite to the source region; and a trench gate extending in depth in the semiconductor body through the body region and the source region. The trench gate includes a dielectric region of porous silicon oxide buried in the semiconductor body, and a gate conductive region extending between the dielectric region of porous silicon oxide and the first side.

Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

Abstract: A semiconductor device includes: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.

Abstract: A semiconductor device comprising: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.

Abstract: An integrated device includes a semiconductor body including an STI insulating structure that laterally delimits first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. A power component, formed in the second active area, includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region. The insulating region is arranged between the body region and the drain-contact region and has a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.

Abstract: For manufacturing an integrated electronic device, a protection layer, of a first material, is formed over a body having a non-planar surface; a first dielectric layer, of a second material, is formed over the protection layer, the second material being selectively etchable with respect to the first material; an intermediate layer, of a third material, is formed over the first dielectric layer, the third material being selectively etchable with respect to the second material; a second dielectric layer, of a fourth material, is formed over the intermediate layer, the fourth material being selectively etchable with respect to the third material; vias are formed through the second dielectric layer, the intermediate layer, the first dielectric layer, and the protection layer; and electrical contacts, of conductive material, are formed in the vias.

Abstract: An integrated device includes a semiconductor body including an STI insulating structure that laterally delimits first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. A power component, formed in the second active area, includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region. The insulating region is arranged between the body region and the drain-contact region and has a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.

Abstract: An embodiment of an integrated device includes a semiconductor body, in which an STI insulating structure is formed, laterally delimiting first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. Formed in the second active area is a power component, which includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region, arranged between the body region and the drain-contact region and having a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.

Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.