Abstract: An embodiment of a vertical-gate transistor disposed on a die includes a first substrate portion of a first conductivity and a second substrate portion of a second conductivity. The die includes front and rear surfaces, the first portion extending from the front surface and the second portion extending from the rear surface to the first portion, at least one drain region of the second conductivity extending from the rear surface, and at least one cell. Each cell includes a source region of the second conductivity extending from the front surface, a conductive gate region extending from the front surface to a gate depth, a conductive field-plate region extending from the front surface to a field depth, a gate-insulating layer that insulates the gate region, and a plate-insulating layer that insulates the field-plate region. An intermediate insulating layer insulates the gate region from the field-plate region.

Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.

Abstract: An embodiment of an integrated device includes a semiconductor body, in which an STI insulating structure is formed, laterally delimiting first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. Formed in the second active area is a power component, which includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region, arranged between the body region and the drain-contact region and having a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.