Patents by Inventor Simone Severi
Simone Severi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10626457Abstract: Arrays of integrated optical devices and their methods for production are provided. The devices include an integrated bandpass filter layer that comprises at least two multi-cavity filter elements with different central bandpass wavelengths. The device arrays are useful in the analysis of highly multiplexed optical reactions in large numbers at high densities, including biochemical reactions, such as nucleic acid sequencing reactions. The devices provide for the efficient and reliable coupling of optical excitation energy from an optical source to the optical reactions. Optical signals emitted from the reactions can thus be measured with high sensitivity and discrimination. The device arrays are well suited for miniaturization and high throughput.Type: GrantFiled: October 28, 2016Date of Patent: April 21, 2020Assignee: Pacific Biosciences of California, Inc.Inventors: Ravi Saxena, Annette Grot, Nicolaas Tack, Pilar Gonzalez, Bert Du Bois, Simone Severi
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Publication number: 20190195827Abstract: Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.Type: ApplicationFiled: December 20, 2018Publication date: June 27, 2019Applicant: IMEC VZWInventors: Koen Martens, Nadine Collaert, Eddy Kunnen, Simone Severi
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Patent number: 10267733Abstract: The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. The device includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer. The first layer includes a detector element. The second layer includes a rejection filter. The third layer is fabricated from dielectric material. The fourth layer is an optical waveguide configured and positioned such that a top surface of the fourth layer is illuminated with an evanescent tail of excitation light guided by the optical waveguide when the fluorescent tags are present. The fifth layer includes a microfluidic channel. The optical waveguide is configured and positioned such that the microfluidic channel is illuminated with the evanescent tail. The detector element is positioned such that light from activated fluorescent tags can be received.Type: GrantFiled: May 22, 2015Date of Patent: April 23, 2019Assignee: IMEC VZWInventors: Pol Van Dorpe, Liesbet Lagae, Peter Peumans, Andim Stassen, Philippe Helin, Bert Du Bois, Simone Severi
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Publication number: 20170145498Abstract: Arrays of integrated optical devices and their methods for production are provided. The devices include an integrated bandpass filter layer that comprises at least two multi-cavity filter elements with different central bandpass wavelengths. The device arrays are useful in the analysis of highly multiplexed optical reactions in large numbers at high densities, including biochemical reactions, such as nucleic acid sequencing reactions. The devices provide for the efficient and reliable coupling of optical excitation energy from an optical source to the optical reactions. Optical signals emitted from the reactions can thus be measured with high sensitivity and discrimination. The device arrays are well suited for miniaturization and high throughput.Type: ApplicationFiled: October 28, 2016Publication date: May 25, 2017Inventors: Ravi SAXENA, Annette GROT, Nicolaas TACK, Pilar GONZALEZ, Bert DU BOIS, Simone SEVERI
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Publication number: 20170082544Abstract: The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. The device includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer. The first layer includes a detector element. The second layer includes a rejection filter. The third layer is fabricated from dielectric material. The fourth layer is an optical waveguide configured and positioned such that a top surface of the fourth layer is illuminated with an evanescent tail of excitation light guided by the optical waveguide when the fluorescent tags are present. The fifth layer includes a microfluidic channel. The optical waveguide is configured and positioned such that the microfluidic channel is illuminated with the evanescent tail. The detector element is positioned such that light from activated fluorescent tags can be received.Type: ApplicationFiled: May 22, 2015Publication date: March 23, 2017Applicant: IMEC VZWInventors: Pol Van Dorpe, Liesbet Lagae, Peter Peumans, Andim Stassen, Philippe Helin, Bert Du Bois, Simone Severi
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Patent number: 9217861Abstract: Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror elements arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt angle range, and each micro-mirror element in the second section has a second tilt angle range, with the first tilt angle range being less than the second tilt angle range.Type: GrantFiled: January 18, 2013Date of Patent: December 22, 2015Assignee: IMEC VZWInventors: Murali Jayapala, Geert Van der Plas, Veronique Rochus, Xavier Rottenberg, Simone Severi
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Patent number: 9201241Abstract: A built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens is described. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles to provide a capacitance-reference angle relationship. From the capacitance values, an interpolation step is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured. For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use.Type: GrantFiled: January 21, 2013Date of Patent: December 1, 2015Assignee: IMECInventors: Murali Jayapala, Geert Van Der Plas, Veronique Rochus, Xavier Rottenberg, Simone Severi, Stéphane Donnay
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Publication number: 20140368920Abstract: Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror element arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt axis range, and each micro-mirror element in the second section has a second tilt axis range, with the first tilt axis range being less than the second tilt axis range.Type: ApplicationFiled: January 18, 2013Publication date: December 18, 2014Applicant: IMEC VZWInventors: Murali Jayapala, Geert Van der Plas, Veronique Rochus, Xavier Rottenberg, Simone Severi
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Patent number: 8536662Abstract: A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.Type: GrantFiled: November 29, 2010Date of Patent: September 17, 2013Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Ann Witvrouw, Luc Haspeslagh, Bin Guo, Simone Severi, Gert Claes
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Patent number: 8492273Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.Type: GrantFiled: August 1, 2011Date of Patent: July 23, 2013Assignee: IMECInventors: George Bryce, Simone Severi, Peter Verheyen
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Patent number: 8487386Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.Type: GrantFiled: June 17, 2010Date of Patent: July 16, 2013Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Ajay Jain, Simone Severi, Gert Claes, John Heck
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Patent number: 8383498Abstract: The present invention provides a method (80) for manufacturing a semiconductor tip. The method comprises obtaining (81) a substrate provided with a layer of tip material, providing (82) a doping profile in the layer of tip material, the doping profile comprising a tapered-shaped region of a first dopant concentration, undoped or lightly doped, e.g. having a dopant concentration of 1017 cm?3 or lower, surrounded by a region of a second dopant concentration, highly doped, e.g. having a dopant concentration above 1017 cm?3, the first dopant concentration being lower than the second dopant concentration, and isotropically etching (83) the layer of tip material by using an etch chemistry for which the etch rate of tip material with the second dopant concentration is substantially higher than the etch rate of the tip material with the first dopant concentration.Type: GrantFiled: August 29, 2008Date of Patent: February 26, 2013Assignee: IMECInventor: Simone Severi
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Patent number: 8207030Abstract: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si nMOS and Ge pMOS. By use of a solid phase epitaxial regrowth (SPER) process for the Si nMOS, the thermal budget for the Si nMOS can be lowered to be compatible with Ge pMOS.Type: GrantFiled: April 28, 2009Date of Patent: June 26, 2012Assignee: IMECInventors: David Paul Brunco, Brice De Jaeger, Simone Severi
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Publication number: 20120034762Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.Type: ApplicationFiled: August 1, 2011Publication date: February 9, 2012Applicant: IMECInventors: George Bryce, Simone Severi, Peter Verheyen
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Publication number: 20110127650Abstract: A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.Type: ApplicationFiled: November 29, 2010Publication date: June 2, 2011Applicants: IMEC, KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&DInventors: Ann Witvrouw, Luc Haspeslagh, Bin Guo, Simone Severi, Gert Claes
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Publication number: 20100320606Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.Type: ApplicationFiled: June 17, 2010Publication date: December 23, 2010Applicants: IMEC, KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&DInventors: Ajay Jain, Simone Severi, Gert Claes, John Heck
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Publication number: 20100295159Abstract: The present invention provides a method (80) for manufacturing a semiconductor tip. The method comprises obtaining (81) a substrate provided with a layer of tip material, providing (82) a doping profile in the layer of tip material, the doping profile comprising a tapered-shaped region of a first dopant concentration, undoped or lightly doped, e.g. having a dopant concentration of 1017 cm?3 or lower, surrounded by a region of a second dopant concentration, highly doped, e.g. having a dopant concentration above 1017 cm?3 , the first dopant concentration being lower than the second dopant concentration, and isotropically etching (83) the layer of tip material by using an etch chemistry for which the etch rate of tip material with the second dopant concentration is substantially higher than the etch rate of the tip material with the first dopant concentration.Type: ApplicationFiled: August 29, 2008Publication date: November 25, 2010Applicant: IMECInventor: Simone Severi
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Publication number: 20090272976Abstract: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si NMOS and Ge pMOS. By use of a solid phase epitaxial regrowth (SPER) process for the Si nMOS, the thermal budget for the Si NMOS can be lowered to be compatible with Ge pMOS.Type: ApplicationFiled: April 28, 2009Publication date: November 5, 2009Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)Inventors: David Paul Brunco, Brice De Jaeger, Simone Severi