Patents by Inventor Simone Severi

Simone Severi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10626457
    Abstract: Arrays of integrated optical devices and their methods for production are provided. The devices include an integrated bandpass filter layer that comprises at least two multi-cavity filter elements with different central bandpass wavelengths. The device arrays are useful in the analysis of highly multiplexed optical reactions in large numbers at high densities, including biochemical reactions, such as nucleic acid sequencing reactions. The devices provide for the efficient and reliable coupling of optical excitation energy from an optical source to the optical reactions. Optical signals emitted from the reactions can thus be measured with high sensitivity and discrimination. The device arrays are well suited for miniaturization and high throughput.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 21, 2020
    Assignee: Pacific Biosciences of California, Inc.
    Inventors: Ravi Saxena, Annette Grot, Nicolaas Tack, Pilar Gonzalez, Bert Du Bois, Simone Severi
  • Publication number: 20190195827
    Abstract: Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 27, 2019
    Applicant: IMEC VZW
    Inventors: Koen Martens, Nadine Collaert, Eddy Kunnen, Simone Severi
  • Patent number: 10267733
    Abstract: The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. The device includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer. The first layer includes a detector element. The second layer includes a rejection filter. The third layer is fabricated from dielectric material. The fourth layer is an optical waveguide configured and positioned such that a top surface of the fourth layer is illuminated with an evanescent tail of excitation light guided by the optical waveguide when the fluorescent tags are present. The fifth layer includes a microfluidic channel. The optical waveguide is configured and positioned such that the microfluidic channel is illuminated with the evanescent tail. The detector element is positioned such that light from activated fluorescent tags can be received.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: April 23, 2019
    Assignee: IMEC VZW
    Inventors: Pol Van Dorpe, Liesbet Lagae, Peter Peumans, Andim Stassen, Philippe Helin, Bert Du Bois, Simone Severi
  • Publication number: 20170145498
    Abstract: Arrays of integrated optical devices and their methods for production are provided. The devices include an integrated bandpass filter layer that comprises at least two multi-cavity filter elements with different central bandpass wavelengths. The device arrays are useful in the analysis of highly multiplexed optical reactions in large numbers at high densities, including biochemical reactions, such as nucleic acid sequencing reactions. The devices provide for the efficient and reliable coupling of optical excitation energy from an optical source to the optical reactions. Optical signals emitted from the reactions can thus be measured with high sensitivity and discrimination. The device arrays are well suited for miniaturization and high throughput.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 25, 2017
    Inventors: Ravi SAXENA, Annette GROT, Nicolaas TACK, Pilar GONZALEZ, Bert DU BOIS, Simone SEVERI
  • Publication number: 20170082544
    Abstract: The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. The device includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer. The first layer includes a detector element. The second layer includes a rejection filter. The third layer is fabricated from dielectric material. The fourth layer is an optical waveguide configured and positioned such that a top surface of the fourth layer is illuminated with an evanescent tail of excitation light guided by the optical waveguide when the fluorescent tags are present. The fifth layer includes a microfluidic channel. The optical waveguide is configured and positioned such that the microfluidic channel is illuminated with the evanescent tail. The detector element is positioned such that light from activated fluorescent tags can be received.
    Type: Application
    Filed: May 22, 2015
    Publication date: March 23, 2017
    Applicant: IMEC VZW
    Inventors: Pol Van Dorpe, Liesbet Lagae, Peter Peumans, Andim Stassen, Philippe Helin, Bert Du Bois, Simone Severi
  • Patent number: 9217861
    Abstract: Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror elements arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt angle range, and each micro-mirror element in the second section has a second tilt angle range, with the first tilt angle range being less than the second tilt angle range.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: December 22, 2015
    Assignee: IMEC VZW
    Inventors: Murali Jayapala, Geert Van der Plas, Veronique Rochus, Xavier Rottenberg, Simone Severi
  • Patent number: 9201241
    Abstract: A built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens is described. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles to provide a capacitance-reference angle relationship. From the capacitance values, an interpolation step is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured. For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: December 1, 2015
    Assignee: IMEC
    Inventors: Murali Jayapala, Geert Van Der Plas, Veronique Rochus, Xavier Rottenberg, Simone Severi, Stéphane Donnay
  • Publication number: 20140368920
    Abstract: Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror element arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt axis range, and each micro-mirror element in the second section has a second tilt axis range, with the first tilt axis range being less than the second tilt axis range.
    Type: Application
    Filed: January 18, 2013
    Publication date: December 18, 2014
    Applicant: IMEC VZW
    Inventors: Murali Jayapala, Geert Van der Plas, Veronique Rochus, Xavier Rottenberg, Simone Severi
  • Patent number: 8536662
    Abstract: A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: September 17, 2013
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Ann Witvrouw, Luc Haspeslagh, Bin Guo, Simone Severi, Gert Claes
  • Patent number: 8492273
    Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: July 23, 2013
    Assignee: IMEC
    Inventors: George Bryce, Simone Severi, Peter Verheyen
  • Patent number: 8487386
    Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: July 16, 2013
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Ajay Jain, Simone Severi, Gert Claes, John Heck
  • Patent number: 8383498
    Abstract: The present invention provides a method (80) for manufacturing a semiconductor tip. The method comprises obtaining (81) a substrate provided with a layer of tip material, providing (82) a doping profile in the layer of tip material, the doping profile comprising a tapered-shaped region of a first dopant concentration, undoped or lightly doped, e.g. having a dopant concentration of 1017 cm?3 or lower, surrounded by a region of a second dopant concentration, highly doped, e.g. having a dopant concentration above 1017 cm?3, the first dopant concentration being lower than the second dopant concentration, and isotropically etching (83) the layer of tip material by using an etch chemistry for which the etch rate of tip material with the second dopant concentration is substantially higher than the etch rate of the tip material with the first dopant concentration.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: February 26, 2013
    Assignee: IMEC
    Inventor: Simone Severi
  • Patent number: 8207030
    Abstract: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si nMOS and Ge pMOS. By use of a solid phase epitaxial regrowth (SPER) process for the Si nMOS, the thermal budget for the Si nMOS can be lowered to be compatible with Ge pMOS.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: June 26, 2012
    Assignee: IMEC
    Inventors: David Paul Brunco, Brice De Jaeger, Simone Severi
  • Publication number: 20120034762
    Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.
    Type: Application
    Filed: August 1, 2011
    Publication date: February 9, 2012
    Applicant: IMEC
    Inventors: George Bryce, Simone Severi, Peter Verheyen
  • Publication number: 20110127650
    Abstract: A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.
    Type: Application
    Filed: November 29, 2010
    Publication date: June 2, 2011
    Applicants: IMEC, KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&D
    Inventors: Ann Witvrouw, Luc Haspeslagh, Bin Guo, Simone Severi, Gert Claes
  • Publication number: 20100320606
    Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.
    Type: Application
    Filed: June 17, 2010
    Publication date: December 23, 2010
    Applicants: IMEC, KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&D
    Inventors: Ajay Jain, Simone Severi, Gert Claes, John Heck
  • Publication number: 20100295159
    Abstract: The present invention provides a method (80) for manufacturing a semiconductor tip. The method comprises obtaining (81) a substrate provided with a layer of tip material, providing (82) a doping profile in the layer of tip material, the doping profile comprising a tapered-shaped region of a first dopant concentration, undoped or lightly doped, e.g. having a dopant concentration of 1017 cm?3 or lower, surrounded by a region of a second dopant concentration, highly doped, e.g. having a dopant concentration above 1017 cm?3 , the first dopant concentration being lower than the second dopant concentration, and isotropically etching (83) the layer of tip material by using an etch chemistry for which the etch rate of tip material with the second dopant concentration is substantially higher than the etch rate of the tip material with the first dopant concentration.
    Type: Application
    Filed: August 29, 2008
    Publication date: November 25, 2010
    Applicant: IMEC
    Inventor: Simone Severi
  • Publication number: 20090272976
    Abstract: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si NMOS and Ge pMOS. By use of a solid phase epitaxial regrowth (SPER) process for the Si nMOS, the thermal budget for the Si NMOS can be lowered to be compatible with Ge pMOS.
    Type: Application
    Filed: April 28, 2009
    Publication date: November 5, 2009
    Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)
    Inventors: David Paul Brunco, Brice De Jaeger, Simone Severi