Patents by Inventor Sinan Goktepeli

Sinan Goktepeli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10896958
    Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: January 19, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, George Pete Imthurn, Yun Han Chu, Qingqing Liang
  • Publication number: 20200373315
    Abstract: Certain aspects of the present disclosure are generally directed to non-volatile memory (NVM) and techniques for operating and fabricating NVM. Certain aspects provide a memory cell for implementing NVM. The memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between and having a different doping type than the first and third semiconductor regions. The memory cell also includes a fourth semiconductor region disposed adjacent to and having the same doping type as the third semiconductor region, a first front gate region disposed adjacent to the second semiconductor region, and a first floating front gate region disposed adjacent to the third semiconductor region. In certain aspects, the memory cell includes a back gate region, wherein the second semiconductor region is between the first front gate region and at least a portion of the back gate region.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 26, 2020
    Inventors: Qingqing LIANG, George Pete IMTHURN, Sinan GOKTEPELI, Sivakumar KUMARASAMY
  • Publication number: 20200365740
    Abstract: Certain aspects of the present disclosure are directed to a memory cell implemented using front and back gate regions. One example memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between the first semiconductor region and the third semiconductor region. The memory cell may also include a front gate region disposed above the second semiconductor region, a floating back gate region, a first portion of the floating back gate region being disposed below the second semiconductor region, and a non-insulative region disposed adjacent to the floating back gate region.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 19, 2020
    Inventors: Qingqing LIANG, Peter Graeme CLARKE, George Pete IMTHURN, Sinan GOKTEPELI, Sivakumar KUMARASAMY
  • Patent number: 10840383
    Abstract: Certain aspects of the present disclosure are directed to a memory cell implemented using front and back gate regions. One example memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between the first semiconductor region and the third semiconductor region. The memory cell may also include a front gate region disposed above the second semiconductor region, a floating back gate region, a first portion of the floating back gate region being disposed below the second semiconductor region, and a non-insulative region disposed adjacent to the floating back gate region.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 17, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Qingqing Liang, Peter Graeme Clarke, George Pete Imthurn, Sinan Goktepeli, Sivakumar Kumarasamy
  • Patent number: 10840387
    Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: November 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Fabio Alessio Marino, Sinan Goktepeli, Narasimhulu Kanike, Qingqing Liang, Paolo Menegoli, Francesco Carobolante, Aristotele Hadjichristos
  • Patent number: 10763257
    Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: September 1, 2020
    Assignee: pSemi Corporation
    Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
  • Publication number: 20200266266
    Abstract: A semiconductor device includes a porous silicon layer on a silicon substrate. The semiconductor device also includes a seal layer on the porous silicon layer. The semiconductor device further includes a high charge carrier mobility material layer on the seal layer. The semiconductor device may further include a strain balancing intermediate layer between the seal layer and the high charge carrier mobility material layer. Different high charge carrier mobility materials can be used in the high charge carrier mobility material layer to form different semiconductor devices.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 20, 2020
    Inventors: Sinan GOKTEPELI, Stephen Alan FANELLI, Richard HAMMOND
  • Patent number: 10748934
    Abstract: An integrated circuit device includes a portion of a support wafer (e.g., a handle wafer), silicon on insulator layer, a first active device, and a second active device. The first active device has a first semiconductor thickness in a dielectric layer (e.g., a buried oxide layer). The first active device is on the SOI layer. The second active device has a second semiconductor thickness in the same dielectric layer as the first active device. The supporting wafer supports the first active device and the second active device. The second active device is also on the SOI layer. The first and second thicknesses are different from one another.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: August 18, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Qingqing Liang, Stephen Alan Fanelli, Sinan Goktepeli
  • Publication number: 20200235107
    Abstract: Antifuse memory cells as well as other applications may provide advantages of conventional approaches. In some examples, a metal backside gate or contact may be formed in the insulator layer opposite the front side contacts and circuits. The metal backside gate or contact may allow a higher voltage on a low resistance and capacitance lie to be applied directly to the dielectric layer of the antifuse to more quickly breakdown the dielectric and program the antifuse.
    Type: Application
    Filed: January 14, 2020
    Publication date: July 23, 2020
    Inventors: Sinan GOKTEPELI, George Pete IMTHURN, Sivakumar KUMARASAMY
  • Patent number: 10707866
    Abstract: A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a first shared drain/source region of the multi-gate active device. The dual sided contact switch has a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The dual sided contact switch also has a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region, and also between the second independent drain/source region and the second shared drain/source region.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Qingqing Liang, Ravi Pramod Kumar Vedula, George Peter Imthurn, Christopher Nelles Brindle, Sinan Goktepeli
  • Publication number: 20200204175
    Abstract: A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a first shared drain/source region of the multi-gate active device. The dual sided contact switch has a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The dual sided contact switch also has a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region, and also between the second independent drain/source region and the second shared drain/source region.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Qingqing LIANG, Ravi Pramod Kumar VEDULA, George Pete IMTHURN, Christopher Nelles BRINDLE, Sinan GOKTEPELI
  • Publication number: 20200185522
    Abstract: A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.
    Type: Application
    Filed: February 11, 2020
    Publication date: June 11, 2020
    Inventors: Qingqing LIANG, Ravi Pramod Kumar VEDULA, Sivakumar KUMARASAMY, George Pete IMTHURN, Sinan GOKTEPELI
  • Patent number: 10680086
    Abstract: A heterojunction bipolar transistor is integrated on radio frequency (RF) dies of different sizes. The heterojunction bipolar transistor includes an emitter on a first-side of a semiconductor-on-insulator (SOI) layer of an SOI substrate. The emitter is accessed from the first-side while a collector is accessed from a second-side of the SOI substrate. One or more portions of a base of the heterojunction bipolar transistor is between the emitter and one or more portions of the collector. The heterojunction bipolar transistor also includes a compound semiconductor layer between the collector and the emitter. The compound semiconductor layer carries a charge between the emitter and the collector.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 9, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, George Pete Imthurn, Stephen Alan Fanelli
  • Publication number: 20200135766
    Abstract: A CMOS process is disclosed for manufacturing an integrated circuit including both MOSFETS and GaN HEMT devices. Each GaN HEMT device resides within an oxidized window that exposes a silicon substrate having a <111> crystal lattice orientation.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: Ranadeep Dutta, Sinan Goktepeli, Antonino Scuderi, George Pete Imthurn
  • Patent number: 10637411
    Abstract: A radio frequency integrated circuit (RFIC) includes multi-finger transistors including discrete diffusion regions and interconnected within a reconfigured form factor as a single switch transistor. The RFIC also includes a source bus having a first plurality of source fingers coupled to each source region of the multi-finger transistors and a second plurality of source fingers orthogonally coupled to the first plurality of source fingers. The second plurality of source fingers couple the discrete diffusion regions in parallel. The RFIC also includes a drain bus having a first plurality of drain fingers coupled to each drain region of the multi-finger transistors and a second plurality of drain fingers orthogonally coupled to the first plurality of drain fingers. The second plurality of drain fingers electrically couple the discrete diffusion regions in parallel. The RFIC further includes a plurality of interconnected body contacts to bias a body of each of the multi-finger transistors.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: April 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Ravi Pramod Kumar Vedula, Sinan Goktepeli, George Pete Imthurn
  • Patent number: 10608124
    Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Fabio Alessio Marino, Narasimhulu Kanike, Plamen Vassilev Kolev, Qingqing Liang, Paolo Menegoli, Francesco Carobolante, Aristotele Hadjichristos
  • Patent number: 10600894
    Abstract: A Bipolar Junction Transistor (BJT) comprises an emitter, a collector, and a base between the emitter and the collector. The BJT also comprises an emitter contact on a first side of the BJT, a base contact on the first side of the BJT, and a collector contact on a second side of the BJT. The BJT further comprises a Deep Trench Isolation (DTI) region extending from the first side of the BJT to the second side of the BJT.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Plamen Vassilev Kolev, Peter Graeme Clarke
  • Patent number: 10600910
    Abstract: An integrated circuit is described. The integrated circuit includes a metal oxide semiconductor field effect transistor (MOSFET). The MOSFET is on a first surface of an insulator layer of the integrated circuit. The MOSFET including a source region, a drain region, and a front gate. The MOSFET also includes an extended drain region between the drain region and a well proximate the front gate. The integrated circuit also includes back gates on a second surface opposite the first surface of the insulator layer. The back gates are overlapped by the extended drain region.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Qingqing Liang, Ravi Pramod Kumar Vedula, Sivakumar Kumarasamy, George Pete Imthurn, Sinan Goktepeli
  • Publication number: 20200091148
    Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 19, 2020
    Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
  • Publication number: 20200091294
    Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Inventors: Sinan GOKTEPELI, George Pete IMTHURN, Yun Han CHU, Qingqing LIANG