Abstract: Fabrication methods and structures for forming integrated circuit (IC) porous semiconductor (?-Semi) isolation structures such as shallow trench isolation (STI) and/or deep trench isolation (DTI) structures. The methods speed up IC front-end-of-line processing and decrease the cost of IC fabrication. In general, exposed portions of a semiconductor layer are subjected to an electrochemical etching to form ?-Semi isolation structures; in essence, the in situ semiconductor is restructured to ?-Semi. The characteristics of ?-Semi, particularly mesoporous ?-Semi and microporous ?-Semi, include good electrical insulation as well as hole trapping capability. Accordingly, ?-Semi used for STI and/or DTI structures provides excellent electrical isolation. A first embodiment comprises a “pre-FET” ?-Semi isolation structure, fabricated before formation of gate, drain, and source structures or regions of a field-effect transistor (FET).

Abstract: Nano-pillar field-effect transistor (FET) structure that include one or more of the following characteristics: vertical device structure and vertical current flow; vertically displaced source and drain regions; different nanowire/nanosheet geometries and dimensions for different nano-pillar embodiments; and/or body contacts made through wide nano-pillar structures. In addition, by utilizing layer transfer techniques, direct access to drain contacts of a nano-pillar FET structure is available, which enables a significant improvement in transistor performance (e.g., lower RON resistance, faster switching speed). An additional advantage of the novel nano-pillar FET structures is that available top and bottom contacts may be used in various 3-D integrated circuit structures, such as by using layer transfer and/or hybrid bonding.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: High-voltage transistors that may be fabricated in a standard low-voltage process. Embodiments include integrated circuits that combine, in a unitary structure, an LDMOS FET device that includes one or more dummy polysilicon structures (DPS's) overlying a drift region and comparable in configuration to the FET gate, and interstitial implant resistance pockets (IRP) formed within the drift region between the gate and an adjacent DPS and between each pair of adjacent DPS's. The IRPs may be augmented with floating contacts to remove heat from the drift region and provide additional shielding of the drain contact from the nearest edge of the gate. The IRPs may be biased to modulate the conductivity of the drift region. The DPS's may be biased to modulate the conductivity of the drift region, and in such a way as to protect each DPS from excessive and potentially destructive voltages.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: Single-chip solutions that result in high capacitance and/or inductance densities. Embodiments provide relatively large capacitance and/or inductance values for applications utilizing DC and/or sub-KHz signals up to RF signals. Embodiments may include an integrated circuit having a substrate having a backside, a substructure formed on the substrate, and a superstructure formed on the substructure and having a metallization layer, the integrated circuit further including at least one backside deep trench capacitor structure including: one or more trenches formed in the backside of the substrate and lined with a first conductive layer, a dielectric, and a second conductive layer; a first electrical connection between the first conductive layer and a first portion of the metallization layer; and a second electrical connection between the second conductive layer and a second portion of the metallization layer.

Abstract: Antenna structures that can be located in close proximity with respect to an associated RFFE IC regardless of antenna element size. An antenna structure, including a grid or planar antenna or an array of antenna elements, is co-fabricated as part of or with one or more associated RFFE ICs using 3-D stacking of IC dies, either directly or as part of an embedded die packaging technology. Some embodiments include a combinable co-fabricated antenna element, including at least one internally co-fabricated RF antenna element configured to be electrically connectable to a corresponding RF antenna element in a second combinable co-fabricated antenna element by means of 3-D integrated circuit stacking. Some embodiments include a plurality of combinable co-fabricated antenna elements coupled together by means of 3-D integrated circuit stacking such that the antenna elements form a grid antenna or comprise an array of antenna patches.

Abstract: Compact polysilicon resistor structures, particularly for RF ICs, and methods of fabricating such structures. Embodiments include three-dimensional (3-D) IC structures that include a 3-D resistor configuration comprising disjointed polysilicon segments spaced by at least one IC substrate and connected by one or more conductive through-substrate vias (TSVs). Compared to the prior art, embodiments of the present invention provide a reduction in IC area required for a polysilicon resistor and result in the same performance while maintaining low parasitic capacitance. For example, by taking advantage of the substrate cross-sectional height, embodiments of the invention can achieve the same resistive performance while reducing area allocation by more than 30%.

Abstract: Single-chip solutions and related methods that result in much higher capacitance densities than is achievable with current on-chip solutions and which reduce consumption of planar area of a mounting structure. Embodiments of the present invention use vertical stacking to affix one or more discrete embeddable capacitors to an IC chip superstructure or base structure, and either sequentially or concurrently form electrical connections between the discrete embeddable capacitors and the IC chip. The inventive processes are compatible with CMOS fabrication temperatures for the IC chip while allowing use of capacitors that are fabricated using other processes that may involve much higher temperatures. The inventive processes allow connection of relatively large capacitances (e.g., ˜0.5 ?F-1 ?F) to an IC chip without increasing the 2-D footprint of the IC chip.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: A radio frequency (RF) front-end (RFFE) device includes a die having a front-side dielectric layer on an active device. The active device is on a first substrate. The RFFE device also includes a microelectromechanical system (MEMS) device. The MEMS device is integrated on the die at a different layer than the active device. The MEMS device includes a cap layer composed of a cavity in the front-side dielectric layer of the die. The cavity in the front-side dielectric layer is between the first substrate and a second substrate. The cap is coupled to the front-side dielectric layer.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having a backside gate contact. An example semiconductor device generally includes a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region and wherein the gate region is disposed adjacent to the channel region. The semiconductor device further includes a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.

Abstract: A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.

Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.