Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

Abstract: An integrated circuit is described. The integrated circuit includes a metal oxide semiconductor field effect transistor (MOSFET). The MOSFET is on a first surface of an insulator layer of the integrated circuit. The MOSFET including a source region, a drain region, and a front gate. The MOSFET also includes an extended drain region between the drain region and a well proximate the front gate. The integrated circuit also includes back gates on a second surface opposite the first surface of the insulator layer. The back gates are overlapped by the extended drain region.

Abstract: A heterojunction bipolar transistor is integrated on radio frequency (RF) dies of different sizes. The heterojunction bipolar transistor includes an emitter on a first-side of a semiconductor-on-insulator (SOI) layer of an SOI substrate. The emitter is accessed from the first-side while a collector is accessed from a second-side of the SOI substrate. One or more portions of a base of the heterojunction bipolar transistor is between the emitter and one or more portions of the collector. The heterojunction bipolar transistor also includes a compound semiconductor layer between the collector and the emitter. The compound semiconductor layer carries a charge between the emitter and the collector.

Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

Abstract: A radio frequency integrated circuit switch includes a semiconductor die with a transistor having a gate on a first-side (e.g., front-side) of the semiconductor die. The semiconductor die may include a bulk semiconductor substrate or wafer (e.g., silicon substrate or wafer). The semiconductor die may also include a first deep trench isolation (DTI) region that extends from the front-side to a backside opposite the front-side of the semiconductor die. The radio frequency integrated circuit switch further includes a body contact layer on the backside of the semiconductor die. The body contact layer is coupled to a backside of a body of the transistor. The body of the transistor may have a first P-type region (e.g., a P+ region).

Abstract: A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switch field effect transistor (FET), including a source region, a drain region, a body region, and a gate. The RFIC also includes a body bypass resistor coupled between the gate and the body region. The RFIC further includes a gate isolation resistor coupled between the gate and the body region. The RFIC also includes a diode coupled between the body bypass resistor and the gate isolation resistor.

Abstract: In certain aspects, a silicon-on-insulator device comprises a back insulating layer and a semiconductor layer on the back insulating layer. The semiconductor layer includes a source region of a first conductive type having a front source surface and a back source surface, a channel region of a second conductive type have a front channel surface and a back channel surface, and a drain region of the first conductive type. The silicon-on-insulator device further comprises a gate insulating layer on the front channel surface of the channel region and a back silicidation layer on at least a portion of the back source surface and a portion of back channel surface.

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.

Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region.

Abstract: A low noise amplifier (LNA) device includes a first transistor on a semiconductor on insulator (SOI) layer. The first transistor includes a source region, a drain region, and a gate. The LNA device also includes a first-side gate contact coupled to the gate. The LNA device further includes a second-side source contact coupled to the source region. The LNA device also includes a second-side drain contact coupled to the drain region.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include a back-bias metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the back-bias metallization. The integrated RF circuit structure may further include a handle substrate on a front-side dielectric layer on the active device.

Abstract: An integrated circuit device includes only semiconductor devices with a same first polarity on one side of an insulator layer and only semiconductor devices with a different second polarity on an opposite side of the insulator layer to reduce size and complexity of the integrated circuit device as well as reducing the process steps associated with fabricating the integrated circuit device. Shared contacts between backside source/drain regions or spacers of the semiconductor devices with the first polarity and front-side source/drain regions or spacers of the semiconductor devices with the first polarity are used to connect the semiconductor devices on opposite sides of the insulator layer.

Abstract: Certain aspects of the present disclosure provide a memory device. One example memory device generally includes a first semiconductor region having a first region, a second region, and a third region, the second region being between the first region and the third region and having a different doping type than the first region and the third region. In certain aspects, the memory device also includes a first non-insulative region, a first insulative region being disposed between the first non-insulative region and the first semiconductor region. In certain aspects, the memory device may include a second non-insulative region, and a second insulative region disposed between the second region and the second non-insulative region, wherein the first insulative region and the second insulative region are disposed adjacent to opposite sides of the second region.

Abstract: A radio frequency (RF) front-end (RFFE) device includes a die having a front-side dielectric layer on an active device. The active device is on a first substrate. The RFFE device also includes a microelectromechanical system (MEMS) device. The MEMS device is integrated on the die at a different layer than the active device. The MEMS device includes a cap layer composed of a cavity in the front-side dielectric layer of the die. The cavity in the front-side dielectric layer is between the first substrate and a second substrate. The cap is coupled to the front-side dielectric layer.

Abstract: A resistor may include a semiconductor layer having a source region, a drain region, and a channel region. The channel region may be between the source region and the drain region. The channel region may have a same polarity as the source region and the drain region. The resistor may further include a first inter-metal dielectric (IMD) layer on the channel region. The resistor may further include a front-side gate shield on the first IMD layer. The front-side gate shield may overlap the channel region.

Abstract: A method of constructing a layer transferred radio frequency (RF) filter-on-insulator wafer includes exposing a front-side of a bulk RF wafer to a laser light source to form a modified layer at a predetermined depth along a horizontal length of the bulk RF wafer. The method also includes bonding the front-side of the bulk RF wafer to a front-side of a semiconductor handle wafer through an insulator layer. The method further includes forming an RF filter layer from the bulk RF wafer. The method also includes selectively etching away the modified layer from the RF filter layer to the predetermined depth to complete the layer transferred RF filter-on-insulator wafer.

Abstract: A resistor may include a semiconductor layer having a source region, a drain region, and a channel region. The channel region may be between the source region and the drain region. The channel region may have a same polarity as the source region and the drain region. The resistor may further include a first inter-metal dielectric (IMD) layer on the channel region. The resistor may further include a front-side gate shield on the first IMD layer. The front-side gate shield may overlap the channel region.

Abstract: A semiconductor device includes a porous silicon layer on a silicon substrate. The semiconductor device also includes a seal layer on the porous silicon layer. The semiconductor device further includes a high charge carrier mobility material layer on the seal layer. The semiconductor device may further include a strain balancing intermediate layer between the seal layer and the high charge carrier mobility material layer. Different high charge carrier mobility materials can be used in the high charge carrier mobility material layer to form different semiconductor devices.

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.