Abstract: A semiconductor structure for manufacturing a semiconductor package device is provided. The semiconductor structure includes a carrier and a dielectric layer. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer. The dielectric layer is formed on the first surface of the carrier. The carrier supports the dielectric layer.

Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.

Abstract: A semiconductor structure for manufacturing a semiconductor package device is provided. The semiconductor structure includes a carrier and a dielectric layer. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer. The dielectric layer is formed on the first surface of the carrier. The carrier supports the dielectric layer.

Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer.

Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.

Abstract: A semiconductor substrate includes a device carrier, a plurality of stiffener structures and a plurality of spaced areas. The device carrier includes a plurality of trace layout units and a periphery around the trace layout units. The stiffener structures are disposed on the device carrier along the periphery of the trace layout units. The spaced areas are disposed between the stiffener structures.

Abstract: A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes a device carrier and a stiffener structure. The device carrier includes at least one insulating layer and at least conductive layer defining at least one trace layout unit. The stiffener structure is disposed on the device carrier, surrounding the periphery of the at least one trace layout unit. The stiffener structure is disposed away from the periphery of the at least one trace layout unit, forming a cavity with the device carrier. The shape and disposition of the stiffener structure enhance the strength of the semiconductor package, impeding flexure to the semiconductor package.

Abstract: Methods and apparatus pertaining to scanning or copying documents are provided. Sheet media are individually transported away from an input location. Optical scanning of the sheet media is initiated in accordance with detecting the passage of leading edges of the sheet media. Electronic signals resulting from the scanning are automatically analyzed to detect trailing edges of overlapping sheet media. A user notification is issued if a multiple sheet pick event is detected. A user can resume scanning or copying of a multiple sheet document at the location where the multiple sheet pick occurred.

Abstract: A door or window assembly (10) is provided. The door or window assembly (10) includes: a track assembly (12); a first leaf (14) slidable along the track assembly (12) in a plane of the first leaf (14) between a first position and a second position; a second leaf (16) moveably coupled to the track assembly (12); and a third leaf (20) pivotally coupled to the second leaf (16). The first leaf (14) is arranged to engage the second leaf (16) to form a combined leaf (86) when the first leaf (14) is in the second position and the combined leaf (86) is arranged to be foldable against the third leaf (20).

Abstract: A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.

Abstract: A door or window assembly (10) is provided. The door or window assembly (10) includes: a track assembly (12); a first leaf (14) slidable along the track assembly (12) in a plane of the first leaf (14) between a first position and a second position; a second leaf (16) moveably coupled to the track assembly (12); and a third leaf (20) pivotally coupled to the second leaf (16). The first leaf (14) is arranged to engage the second leaf (16) to form a combined leaf (86) when the first leaf (14) is in the second position and the combined leaf (86) is arranged to be foldable against the third leaf (20).

Abstract: A semiconductor package includes a trace molding compound layer and a chip molding compound layer. The trace molding compound layer has a first surface and a second surface, wherein the trace molding compound layer encapsulates a plurality of traces and studs between the first and second surface. The chip molding compound layer has a first surface and a second surface, wherein the chip molding compound layer encapsulates a semiconductor chip between the first and second surface of the chip molding compound layer. The chip molding compound layer is disposed on the trace molding compound layer, the second surface of the chip molding compound layer adheres to the first surface of the trace molding compound layer, and the chip molding compound layer and the trace molding compound layer comprise substantially the same molding compound material.

Abstract: A manufacturing method includes the follow steps. Firstly, a carrier is provided. Then, a plurality of traces are formed on the carrier. Then, a trace molding compound layer is formed on the carrier by a first molding process. Then, the carrier is removed from the trace molding compound layer to expose an etched surface of the trace molding compound layer and trace upper surfaces of the traces. Then, at least a chip is disposed on the etched surface of the trace molding compound layer and the chip is connected to the trace upper surfaces. Then, a chip molding compound layer is formed on the etched surface by a second molding process substantially similar to the first molding process, wherein the chip molding compound layer and the trace molding compound layer are formed of substantially the same molding compound material.

Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.

Abstract: A manufacturing method of semiconductor substrate includes following steps: providing a base layer; forming a plurality of traces on the base layer; forming a plurality of studs correspondingly on the traces; forming a molding material layer on the base layer to encapsulate the traces and studs; forming a concave portion on the molding material layer; and, removing the base layer.

Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.