Patents by Inventor Siu Lung Chan

Siu Lung Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7447081
    Abstract: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: November 4, 2008
    Assignee: Sandisk Corporation
    Inventor: Siu Lung Chan
  • Publication number: 20080253185
    Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
    Type: Application
    Filed: June 20, 2008
    Publication date: October 16, 2008
    Inventors: Raul-Adrian Cernea, Siu Lung Chan
  • Patent number: 7391645
    Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: June 24, 2008
    Assignee: Sandisk Corporation
    Inventors: Raul-Adrian Cernea, Siu Lung Chan
  • Patent number: 7391646
    Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: June 24, 2008
    Assignee: Sandisk Corporation
    Inventors: Raul-Adrian Cernea, Siu Lung Chan
  • Patent number: 7327619
    Abstract: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: February 5, 2008
    Assignee: Sandisk Corporation
    Inventors: Siu Lung Chan, Raul-Adrian Cernea
  • Patent number: 7324393
    Abstract: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: January 29, 2008
    Assignee: Sandisk Corporation
    Inventors: Siu Lung Chan, Raul-Adrian Cernea
  • Patent number: 7310255
    Abstract: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: December 18, 2007
    Assignee: SanDisk Corporation
    Inventor: Siu Lung Chan
  • Patent number: 7251160
    Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: July 31, 2007
    Assignee: Sandisk Corporation
    Inventors: Yan Li, Seungpil Lee, Siu Lung Chan
  • Patent number: 7224614
    Abstract: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: May 29, 2007
    Assignee: Sandisk Corporation
    Inventor: Siu Lung Chan
  • Patent number: 7173854
    Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: February 6, 2007
    Assignee: SanDisk Corporation
    Inventors: Raul-Adrian Cernea, Siu Lung Chan
  • Patent number: 7170784
    Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: January 30, 2007
    Assignee: SanDisk Corporation
    Inventors: Raul-Adrian Cernea, Siu Lung Chan