Patents by Inventor Siu Waf Low
Siu Waf Low has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6958537Abstract: A semiconductor device package is disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: August 4, 2004Date of Patent: October 25, 2005Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Publication number: 20050116337Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: ApplicationFiled: January 3, 2005Publication date: June 2, 2005Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Shuangwu Huang, Wei Zhou
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Patent number: 6882021Abstract: Packaged microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, the device includes an image sensor die having a first side with a bond-pad, an active area on the first side, and a second side opposite the first side. The device further includes a window at the first side of the image sensor die and a lead mounted to the second side of the image sensor die. The window is radiation transmissive and positioned over the active area of the image sensor die. The lead is electrically coupled to the bond-pad on the image sensor die.Type: GrantFiled: August 29, 2003Date of Patent: April 19, 2005Assignee: Micron Technology, Inc.Inventors: Suan Jeung Boon, Yong Poo Chia, Min Yu Chan, Meow Koon Eng, Siu Waf Low, Swee Kwang Chua
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Patent number: 6856155Abstract: A testing scheme for ball-grid array devices of different sizes where the same ball-grid pattern may be tested using the same set of test adapters. A testing scheme includes providing a plurality of devices having a predetermined pattern of solder balls attached, providing a plurality of adapters secured to a test board, each of the adapters including a plurality of test contacts arranged in a pattern corresponding to the predetermined pattern of solder balls, removably attaching the plurality of devices to a device holding apparatus such that the predetermined pattern of solder balls on the devices corresponds to the predetermined pattern of test contacts on the plurality of adapters, then positioning the device holding apparatus to bring the plurality of solder balls in contact with the plurality of test contacts.Type: GrantFiled: October 7, 2002Date of Patent: February 15, 2005Assignee: Micron Technology, Inc.Inventors: Wuu Yean Tay, Yong Kian Tan, Yong Poo Chia, Siu Waf Low, Suan Jeung Boon, Soon Huat Goh
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Publication number: 20040238909Abstract: Packaged microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, the device includes an image sensor die having a first side with a bond-pad, an active area on the first side, and a second side opposite the first side. The device further includes a window at the first side of the image sensor die and a lead mounted to the second side of the image sensor die. The window is radiation transmissive and positioned over the active area of the image sensor die. The lead is electrically coupled to the bond-pad on the image sensor die.Type: ApplicationFiled: August 29, 2003Publication date: December 2, 2004Inventors: Suan Jeung Boon, Yong Poo Chia, Min Yu Chan, Meow Koon Eng, Siu Waf Low, Swee Kwang Chua
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Patent number: 6825553Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: September 5, 2003Date of Patent: November 30, 2004Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou
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Publication number: 20040229400Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: ApplicationFiled: June 22, 2004Publication date: November 18, 2004Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Shuangwu Huang, Wei Zhou
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Publication number: 20040084741Abstract: A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.Type: ApplicationFiled: October 23, 2003Publication date: May 6, 2004Inventors: Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo, Swee Kwang Chua, Siu Waf Low
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Publication number: 20040046250Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: ApplicationFiled: September 5, 2003Publication date: March 11, 2004Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Shuangwu Huang, Wei Zhou
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Publication number: 20040041221Abstract: A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.Type: ApplicationFiled: August 28, 2002Publication date: March 4, 2004Inventors: Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo, Swee Kwang Chua, Siu Waf Low
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Publication number: 20040042190Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package includes The package may include a variety of semiconductor dice thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements are also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: ApplicationFiled: August 27, 2002Publication date: March 4, 2004Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Shuangwu Huang
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Publication number: 20040043533Abstract: The present invention defines a packaging implementation providing a multi-chip multi-layer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate. Additional redistribution and interconnect layers above the multi-chip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment the cavities receive the dice with the active surface of the dice facing up wherein metal layer connections are formed and coupled bond pads or other electrical connectors of the dice.Type: ApplicationFiled: August 27, 2002Publication date: March 4, 2004Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Shuangwu Huang, Wei Zhou
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Publication number: 20040032273Abstract: The present invention provides systems and methods which overcome the shortcomings of the prior art by providing a testing scheme wherein ball-grid array devices of different sizes but the same ball-grid pattern may be efficiently and cost-effectively tested using the same set of test adapters.Type: ApplicationFiled: October 7, 2002Publication date: February 19, 2004Inventors: Wuu Yean Tay, Yong Kian Tan, Yong Poo Chia, Siu Waf Low, Suan Jeung Boon, Soon Huat Goh
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Publication number: 20030227079Abstract: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.Type: ApplicationFiled: June 11, 2002Publication date: December 11, 2003Applicant: Micron Technology, Inc.Inventors: Yong Poo Chia, Suan Jeung Boon, Siu Waf Low, Yong Loo Neo, Bok Leng Ser
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Patent number: 6387729Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.Type: GrantFiled: July 6, 2001Date of Patent: May 14, 2002Assignee: Texas Instruments IncorporatedInventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee
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Patent number: 6365833Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.Type: GrantFiled: February 22, 2000Date of Patent: April 2, 2002Assignee: Texas Instruments IncorporatedInventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee
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Publication number: 20020001882Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.Type: ApplicationFiled: July 6, 2001Publication date: January 3, 2002Inventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee
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Patent number: 6236107Abstract: A method and apparatus for fabricating small form factor semiconductor chips having high temperature resistance, good humidity and chemical resistance and good dielectric properties. The semiconductor chip includes a lead frame (10) attached to an integrated circuit die (30) by a lead-on-chip (LOC) method. Wire bonds (40) are employed to connect the integrated circuit die (30) to conduction leads (75) on the lead frame (10). After the wire bonding process, the surface of the wire bonded integrated circuit is encapsulated with a layer of resin (50) using either a direct dispensing method or by a screen printing method. The encapsulated integrated circuit may then be cured and functionally tested.Type: GrantFiled: June 7, 1995Date of Patent: May 22, 2001Assignee: Texas Instruments IncorporatedInventors: Min Yu Chan, Siu Waf Low, Jing Sua Goh
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Patent number: 6137164Abstract: A thin, stacked face-to-face integrated circuit packaging structure includes a chips attached to both major surfaces of a rigid interposer, and interconnected by printed wiring traces and vias to external solder ball contacts attached to the interposer.Type: GrantFiled: September 22, 1999Date of Patent: October 24, 2000Assignee: Texas Instruments IncorporatedInventors: Chee Klang Yew, Siu Waf Low, Min Yu Chan
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Patent number: 6087203Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.Type: GrantFiled: December 19, 1997Date of Patent: July 11, 2000Assignee: Texas Instruments IncorporatedInventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee