Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A non-single-crystal layer has a first section arranged beneath the trench isolation regions and a second section arranged beneath the active device region. The first section of the non-single-crystal layer has a first width in a vertical direction. The second section of the non-single-crystal layer has a second width in the vertical direction that is less than the first width of the first section of the non-single-crystal layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

Abstract: Waveguide structures and methods of fabricating waveguide structures. The waveguide structures are formed using a semiconductor substrate that includes a device layer, a handle wafer, a buried oxide layer between the handle wafer and the device layer, and an epitaxial semiconductor layer over the device layer. First and second trench isolation regions extend through the device layer and the epitaxial semiconductor layer. The first and second trench isolation regions are spaced to define a waveguide core region comprising a section of the device layer and a section of the epitaxial semiconductor layer that are arranged between the first and second trench isolation regions. A first airgap and a second airgap are respectively located in the device layer and the buried oxide layer. The first and second airgaps are arranged beneath the waveguide core region, and the first airgap may be arranged between the second airgap and the waveguide core region.

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions.

Abstract: A method includes forming a sacrificial gate and a stack of materials above a semiconductor substrate, forming a trench in each of the source/drain areas of the device, wherein each trench extends into the semiconductor substrate, forming an empty space under the sacrificial gate structure, the empty space being vertically positioned between the stack of materials and the semiconductor substrate, wherein the empty space is in communication with the trenches, performing a conformal deposition process so as to deposit a conformal layer of a device isolation material adjacent at least the sacrificial gate while at least partially filling the empty space and substantially filling the trenches, and performing a recess etching process to remove at least portions of the conformal layer positioned adjacent the sacrificial gate, thereby defining a recessed upper surface of the device isolation material.