Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. Shallow trench isolation regions extend from a top surface of a semiconductor substrate into the semiconductor substrate. The semiconductor substrate contains single-crystal semiconductor material, and the shallow trench isolation regions are positioned to surround an active device region of the semiconductor substrate. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer has a first section beneath the active device region and a second section beneath the plurality of shallow trench isolation regions. The first section of the polycrystalline layer is located at a different depth relative to the top surface of the semiconductor substrate than the second section of the polycrystalline layer.

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.

Abstract: Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.

Abstract: Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions.

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A first gate electrode has a first plurality of segments arranged in series to define a first non-rectilinear chain. A second gate electrode is arranged adjacent to the first gate electrode. The second gate electrode includes a second plurality of segments arranged in series to define a second non-rectilinear chain. A source/drain region is laterally arranged between the first gate electrode and the second gate electrode.

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. An isolation region is arranged to surround an active device region, which is composed of a semiconductor material. A trench is arranged in the active device region. The trench includes a bottom surface and a sidewall extending from the bottom surface to a top surface of the active device region. A gate electrode of the field-effect transistor has a first section on the top surface of the active device region, a second section on the bottom surface of the trench, and a third section on the sidewall of the trench.

Abstract: Structures for a heterojunction bipolar transistor and methods of fabricating such structures. A hardmask is formed that includes an opening over a first portion of a substrate in a first device region and a shape over a second portion of the substrate in a second device region. An oxidized region in the first portion of the substrate while the shape blocks oxidation of the second portion of the substrate. The oxidized region is subsequently removed from the first portion of the substrate to define a recess. A first base and a first emitter of a first heterojunction bipolar transistor are formed over the first portion of the substrate in the first device region, and a second base and a second emitter of a second heterojunction bipolar transistor are formed in the recess over the second portion of the substrate in the second device region.

Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

Abstract: Structures for a heterojunction bipolar transistor and methods of fabricating such structures. A hardmask is formed that includes an opening over a first portion of a substrate in a first device region and a shape over a second portion of the substrate in a second device region. An oxidized region in the first portion of the substrate while the shape blocks oxidation of the second portion of the substrate. The oxidized region is subsequently removed from the first portion of the substrate to define a recess. A first base and a first emitter of a first heterojunction bipolar transistor are formed over the first portion of the substrate in the first device region, and a second base and a second emitter of a second heterojunction bipolar transistor are formed in the recess over the second portion of the substrate in the second device region.

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A first gate electrode has a first plurality of segments arranged in series to define a first non-rectilinear chain. A second gate electrode is arranged adjacent to the first gate electrode. The second gate electrode includes a second plurality of segments arranged in series to define a second non-rectilinear chain. A source/drain region is laterally arranged between the first gate electrode and the second gate electrode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to through-silicon vias (TSV) for heterogeneous integration of semiconductor device structures and methods of manufacture. The structure includes: a plurality of cavity structures provided in a single substrate; at least one optical device provided on two sides of the single substrate and between the plurality of cavity structures; and a through wafer optical via extending through the substrate, between the plurality of cavity structures and which exposes a backside of the at least one optical device.

Abstract: Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to through-silicon vias (TSV) for heterogeneous integration of semiconductor device structures and methods of manufacture. The structure includes: a plurality of cavity structures provided in a single substrate; at least one optical device provided on two sides of the single substrate and between the plurality of cavity structures; and a through wafer optical via extending through the substrate, between the plurality of cavity structures and which exposes a backside of the at least one optical device.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.