Patents by Inventor Siva Prakash Gurrum
Siva Prakash Gurrum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869820Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.Type: GrantFiled: July 1, 2022Date of Patent: January 9, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack
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Publication number: 20230100709Abstract: An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and >1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.Type: ApplicationFiled: December 5, 2022Publication date: March 30, 2023Inventors: Hung-Yun Lin, Siva Prakash Gurrum
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Patent number: 11538742Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.Type: GrantFiled: April 14, 2020Date of Patent: December 27, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Siva Prakash Gurrum, Manu J. Prakuzhy, Saumya Gandhi
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Patent number: 11521904Abstract: An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and ?1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.Type: GrantFiled: March 11, 2020Date of Patent: December 6, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hung-Yun Lin, Siva Prakash Gurrum
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Publication number: 20220344232Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive connector and a die that has an active side and a non-active side. The active side of the die is connected to the electrically conductive connector via interconnects. A molding compound encapsulates the die and portions of the electrically conductive connector. A thermally conductive contact extends from a thermal hotspot on the die to an entry surface of the molding compound.Type: ApplicationFiled: April 26, 2021Publication date: October 27, 2022Inventors: MANU JOSEPH PRAKUZHY, SIVA PRAKASH GURRUM, BLAKE BARRETT TRAVIS
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Publication number: 20220336304Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack
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Patent number: 11387155Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.Type: GrantFiled: April 27, 2020Date of Patent: July 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack
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Patent number: 11139178Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.Type: GrantFiled: October 15, 2019Date of Patent: October 5, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amit Sureshkumar Nangia, Siva Prakash Gurrum, Janakiraman Seetharaman
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Publication number: 20210287950Abstract: An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and ?1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.Type: ApplicationFiled: March 11, 2020Publication date: September 16, 2021Inventors: Hung-Yun Lin, Siva Prakash Gurrum
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Patent number: 11121049Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.Type: GrantFiled: January 16, 2019Date of Patent: September 14, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Siva Prakash Gurrum, Amit Sureshkumar Nangia
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Publication number: 20210183717Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.Type: ApplicationFiled: April 27, 2020Publication date: June 17, 2021Inventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack
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Publication number: 20200243428Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Inventors: Siva Prakash Gurrum, Manu J. Prakuzhy, Saumya Gandhi
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Patent number: 10622290Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.Type: GrantFiled: July 11, 2018Date of Patent: April 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Siva Prakash Gurrum, Manu J. Prakuzhy, Saumya Gandhi
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Publication number: 20200043753Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.Type: ApplicationFiled: October 15, 2019Publication date: February 6, 2020Inventors: Amit Sureshkumar Nangia, Siva Prakash Gurrum, Janakiraman Seetharaman
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Publication number: 20200020620Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.Type: ApplicationFiled: July 11, 2018Publication date: January 16, 2020Inventors: Siva Prakash Gurrum, Manu J. Prakuzhy, Saumya Gandhi
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Patent number: 10497643Abstract: A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.Type: GrantFiled: May 8, 2018Date of Patent: December 3, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Siva Prakash Gurrum, Manu J Prakuzhy
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Publication number: 20190348346Abstract: A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.Type: ApplicationFiled: May 8, 2018Publication date: November 14, 2019Inventors: SIVA PRAKASH GURRUM, MANU J. PRAKUZHY
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Patent number: 10446414Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.Type: GrantFiled: December 22, 2017Date of Patent: October 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amit Sureshkumar Nangia, Siva Prakash Gurrum, Janakiraman Seetharaman
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Publication number: 20190198352Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Amit Sureshkumar NANGIA, Siva Prakash GURRUM, Janakiraman SEETHARAMAN
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Publication number: 20190172766Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.Type: ApplicationFiled: January 16, 2019Publication date: June 6, 2019Inventors: Siva Prakash Gurrum, Amit Sureshkumar Nangia