Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.

Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.

Abstract: A method of computing a peak current density specification (jpeakspec) for an electrical conductor line of an integrated circuit (IC) resulting from conducting pulsed electrical current represented as a current waveform. An on-time (ton) is identified for the current waveform based on a current density being greater than or equal to (?) a predetermined current density level. The jpeakspec is computed for the electrical conductor line using a jpeakspec modeling equation which includes the ton for the current waveform and a thermal time constant (?) for the electrical conductor line.

Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.

Abstract: A method of computing a peak current density specification (jpeakspec) for an electrical conductor line of an integrated circuit (IC) resulting from conducting pulsed electrical current represented as a current waveform. An on-time (ton) is identified for the current waveform based on a current density being greater than or equal to (?) a predetermined current density level. The jpeakspec is computed for the electrical conductor line using a jpeakspec modeling equation which includes the ton for the current waveform and a thermal time constant (?) for the electrical conductor line.

Abstract: A plastic package (100) in which a semiconductor chip (101) is adhesively (102) attached to a metal stripe (110a) having an agglomerate structure, and electrically connected to bondable and solderable metal stripes (120) having particulate structures; metal stripes (120) are touching metal stripes (110b) of agglomerate structure to form vertical stacks (150); coats of solder (140) are welded to the agglomerate metal stripes (100a and 110b).

Abstract: An electronic package 100 comprising a semiconductor device 105, a heat spreader layer 110, and a thermal interface material layer 115 located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer 120 having heat conductive particles 125 suspended therein. A portion of the particles are exposed on at least one non-planar surface 135 of the resin layer such that the portion of exposed particles 130 occupies a majority of a total area of a horizontal plane 140 of the non-planar surface.

Abstract: A plastic package (100) in which a semiconductor chip (101) is adhesively (102) attached to a metal stripe (110a) having an agglomerate structure, and electrically connected to bondable and solderable metal stripes (120) having particulate structures; metal stripes (120) are touching metal stripes (110b) of agglomerate structure to form vertical stacks (150); coats of solder (140) are welded to the agglomerate metal stripes (100a and 110b).

Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.

Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.

Abstract: An electronic package 100 comprising a semiconductor device 105, a heat spreader layer 110, and a thermal interface material layer 115 located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer 120 having heat conductive particles 125 suspended therein. A portion of the particles are exposed on at least one non-planar surface 135 of the resin layer such that the portion of exposed particles 130 occupies a majority of a total area of a horizontal plane 140 of the non-planar surface.

Abstract: An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer having heat conductive particles suspended therein. A portion of the particles are exposed on at least one non-planar surface of the resin layer such that the portion of exposed particles occupies a majority of a total area of a horizontal plane of the non-planar surface.

Abstract: A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.

Abstract: A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.

Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.

Abstract: An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer having heat conductive particles suspended therein. A portion of the particles are exposed on at least one non-planar surface of the resin layer such that the portion of exposed particles occupies a majority of a total area of a horizontal plane of the non-planar surface.