Abstract: An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the underlying metal hard mask is protected. Thinner hard masks and/or a wider range of etch chemistries may thereby be utilized.

Abstract: A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer.

Abstract: A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer.

Abstract: A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer.

Abstract: A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap.

Abstract: Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.

Abstract: Various embodiment integrate embedded dynamic random access memory with fin field effect transistors. In one embodiment, a first fin structure and at least a second fin structure are formed on a substrate. A deep trench area is formed between the first and second fin structures. A high-k metal gate is formed within the deep trench area. The high-k metal gate includes a high-k dielectric layer and a metal layer. A polysilicon material is deposited within the deep trench area adjacent to the metal layer. The high-k metal gate and the polysilicon material are recessed and etched to an area below a top surface of a substrate insulator layer. A poly strap is formed in the deep trench area. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first and second fin structures are electrically coupled to the poly strap.

Abstract: An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the underlying metal hard mask is protected. Thinner hard masks and/or a wider range of etch chemistries may thereby be utilized.

Abstract: A low-temperature metal gate stack for a field-effect transistor that is electrically activated at temperatures below 1000° C. The metal gate stack is composed of low melting materials that can be deposited by physical vapor deposition (PVD) onto a substrate.

Abstract: A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed.

Abstract: Techniques for improving magnetic device performance are provided. In one aspect, a magnetic device, e.g., a magnetic random access memory device, is provided which comprises a plurality of current carrying lines; and two or more adjacent stacked magnetic toggling devices sharing at least one of the plurality of current carrying lines in common and positioned therebetween. The magnetic device is configured such that at least one of the adjacent magnetic toggling devices toggles mutually exclusively of another of the adjacent magnetic toggling devices. In an exemplary embodiment, the magnetic device comprises a plurality of levels with each of the adjacent stacked magnetic toggling devices residing in a different level.

Abstract: A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.

Abstract: A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap.

Abstract: A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed.

Abstract: A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer.

Abstract: A method for fabricating a microelectronic structure provides for forming a backfilling material layer at least laterally adjacent, and preferably laterally adjoining, a resist layer located over a substrate. Preferably, the resist layer comprises a surface treated resist layer. Optionally, the backfilling material layer may be surface treated similarly to the surface treated resist layer. Under such circumstances: (1) surface portions of the backfilling material layer and resist layer; and (2) remaining portions of the backfilling material layer and resist layer, may be sequentially stripped using a two step etch method, such as a two step plasma etch method. Alternatively, a surface portion of the surface treated resist layer only may be stripped while using a first etch method, and the remaining portions of the resist layer and backfilling material layer may be planarized prior to being simultaneously stripped while using a second etch method.

Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

Abstract: In one embodiment, the invention is a method and apparatus for bitline and contact via integration in magnetic random access memory arrays. One embodiment of a magnetic random access memory according to the present invention includes a magnetic tunnel junction and a top wire that surrounds the magnetic tunnel junction on at least three sides.

Abstract: Techniques for improving magnetic device performance are provided. In one aspect, a magnetic device, e.g., a magnetic random access memory device, is provided which comprises a plurality of current carrying lines; and two or more adjacent stacked magnetic toggling devices sharing at least one of the plurality of current carrying lines in common and positioned therebetween. The magnetic device is configured such that at least one of the adjacent magnetic toggling devices toggles mutually exclusively of another of the adjacent magnetic toggling devices. In an exemplary embodiment, the magnetic device comprises a plurality of levels with each of the adjacent stacked magnetic toggling devices residing in a different level.

Abstract: Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.