Abstract: Disclosed are a lithium-ion supply electrode for real-time microscopic analysis and a method of manufacturing same. The lithium-ion supply electrode includes a solid electrolyte layer including a solid electrolyte, a lithium layer formed on the solid electrolyte layer and including lithium, and a protective layer formed on the lithium layer and including a metal. Therefore, lithium in the electrode does not undergo oxidation in a short time. Therefore, the lithium-ion supply electrode can be used for real-time analysis of structural changes and interfacial reactions of lithium secondary battery materials using a transmission electron microscope.

Abstract: According to one aspect of the invention, a circuit board for a display device includes: a first layer; a first lead line disposed on the first layer; and a sound generator disposed on the first layer, and the sound generator including: a first electrode to receive a first driving voltage; a second electrode to receive a second driving voltage; and a second layer disposed between the first electrode and the second electrode to contract or expand according to the first driving voltage and the second driving voltage; and a first solder to electrically communicate the first lead line and the first electrode.

Abstract: Provided is an electronic device including a semiconductor substrate, a single-crystal first transition metal oxide layer on the semiconductor substrate, and a single-crystal second transition metal oxide layer spaced apart from the semiconductor substrate with the single-crystal first transition metal oxide layer interposed therebetween. The first transition metal oxide layer and the second transition metal oxide layer are in contact with each other. The semiconductor substrate, the first transition metal oxide layer, and the second transition metal oxide layer include different materials from each other. The first transition metal oxide layer and the second transition metal oxide layer have the same crystal direction.

Abstract: A display device includes a display panel including a main area, a first subsidiary area extending from a first side of the main area, and a second subsidiary area extending from a second side of the main area, and a first sound generator disposed on the first subsidiary area and the second subsidiary area of the display panel, where the first sound generator generates a sound by vibrating the first subsidiary area and the second subsidiary area of the display panel.

Abstract: A display device includes a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element disposed on a substrate, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element emit visible light, the fourth light-emitting element emits invisible light, and a size of a light emission area of the fourth light-emitting element is smaller than a size of a light emission area of each of the first to third light-emitting elements in a plan view.

Abstract: The present disclosure relates to a system and method for predicting and detecting the outbreak of a fire.

Abstract: A display device may include: a display panel; a vibration generating device disposed on one surface of the display panel, the vibration generating device configured to generate vibration to be transmitted to the display panel; a panel bottom member disposed between the display panel and the vibration generating device; and a vibration transmitting member disposed in the panel bottom member to at least partially overlap with the vibration generating device in plan view.

Abstract: A method of analyzing a perovskite structure using machine learning, the method comprising the steps of: (a) obtaining an atomic image using an atomic structure simulator; (b) making a CNN model learn the atomic image; and (c) obtaining an atomic image of an actual substance using a TEM or a STEM and then applying the image to the learnt CNN model.

Abstract: A display device includes a display panel including a main area, a first subsidiary area extending from a first side of the main area, and a second subsidiary area extending from a second side of the main area, and a first sound generator disposed on the first subsidiary area and the second subsidiary area of the display panel, where the first sound generator generates a sound by vibrating the first subsidiary area and the second subsidiary area of the display panel.

Abstract: According to one aspect of the invention, a circuit board for a display device includes: a first layer; a first lead line disposed on the first layer; and a sound generator disposed on the first layer, and the sound generator including: a first electrode to receive a first driving voltage; a second electrode to receive a second driving voltage; and a second layer disposed between the first electrode and the second electrode to contract or expand according to the first driving voltage and the second driving voltage; and a first solder to electrically communicate the first lead line and the first electrode.

Abstract: The present disclosure provides methods and apparatus relating to a 5G or pre-5G communication system for supporting a higher data rate than that of a 4G communication system, such as long term evolution (LTE). A method for processing traffic at a core network entity processes traffic includes transmitting a message for requesting assistance information to at least one base station, receiving the assistance information from the at least one base station, splitting the traffic based on the received assistance information, and transmitting the split traffic through a core network. A core network entity includes a transceiver and a processor configured to control the transceiver to transmit a message for requesting assistance information to at least one base station, receive the assistance information from the at least one base station, split traffic based on the received assistance information, and transmit data through the split traffic.

Abstract: A display device may include: a display panel; a vibration generating device disposed on one surface of the display panel, the vibration generating device configured to generate vibration to be transmitted to the display panel; a panel bottom member disposed between the display panel and the vibration generating device; and a vibration transmitting member disposed in the panel bottom member to at least partially overlap with the vibration generating device in plan view.

Abstract: A method of analyzing a perovskite structure using machine learning, the method comprising the steps of: (a) obtaining an atomic image using an atomic structure simulator; (b) making a CNN model learn the atomic image; and (c) obtaining an atomic image of an actual substance using a TEM or a STEM and then applying the image to the learnt CNN model.

Abstract: The present disclosure provides methods and apparatus relating to a 5G or pre-5G communication system for supporting a higher data rate than that of a 4G communication system, such as long term evolution (LTE). A method for processing traffic at a core network entity processes traffic includes transmitting a message for requesting assistance information to at least one base station, receiving the assistance information from the at least one base station, splitting the traffic based on the received assistance information, and transmitting the split traffic through a core network. A core network entity includes a transceiver and a processor configured to control the transceiver to transmit a message for requesting assistance information to at least one base station, receive the assistance information from the at least one base station, split traffic based on the received assistance information, and transmit data through the split traffic.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.