Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

Abstract: Embodiments include methods, and systems of an integrated circuit having electromigration wearout detection circuits. Integrated circuit may include a detection element and a reference element. Detection element is subject to normal operation current. Reference element is not subject to normal operation current. A resistance of detection element is monitored to detect electromigration wearout. The electromigration wearout detection monitoring circuit may be configured to perform: periodically measuring resistance of detection element, calculating resistance change of detection element over a predetermined time period, comparing resistance change of detection element calculated to a predetermined safety threshold, and take mitigation actions when resistance change of detection element exceeds predetermined safety threshold. The mitigation actions may include switching to a redundant circuit of the integrated circuit, shutting down the integrated circuit, and sending a signal to initiate a service call.

Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more first conductors connected to a first electrical connection on the semiconductor device, the first conductor comprising a first material having a positive Seebeck coefficient; and one or more second conductors connected to a second electrical connection on the semiconductor device, the second conductor comprising a second material having a negative Seebeck coefficient. The first conductor and the second conductor conduct electrical current through the semiconductor device and conduct heat away from the semiconductor device.

Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

Abstract: An inverter circuit for reducing runaway current due to applied voltage stress and temperature conditions comprises: first and second field effect transistor (FET) devices of opposite device polarities for driving a connected second stage device having a connected 2nd stage first and second FET devices, each 2nd stage device having a respective input gate terminal. The first FET and second FET devices have a respective output drive terminal, a first conductive structure connects the first FET output drive terminal to the input gate terminal of each the first and second connected FET device and further connects the first FET output drive terminal to the second FET output drive terminal through a ballasting resistor device. A second separate conductive structure connects the second FET output drive terminal to the input gate terminals and includes a path further connecting the second FET output drive terminal to the first FET output drive terminal through the ballasting resistor device.

Abstract: A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more first conductors connected to a first electrical connection on the semiconductor device, the first conductor comprising a first material having a positive Seebeck coefficient; and one or more second conductors connected to a second electrical connection on the semiconductor device, the second conductor comprising a second material having a negative Seebeck coefficient. The first conductor and the second conductor conduct electrical current through the semiconductor device and conduct heat away from the semiconductor device.

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more first conductors connected to a first electrical connection on the semiconductor device, the first conductor comprising a first material having a positive Seebeck coefficient; and one or more second conductors connected to a second electrical connection on the semiconductor device, the second conductor comprising a second material having a negative Seebeck coefficient. The first conductor and the second conductor conduct electrical current through the semiconductor device and conduct heat away from the semiconductor device.

Abstract: Embodiments include methods, and systems of an integrated circuit having electromigration wearout detection circuits. Integrated circuit may include a detection element and a reference element. Detection element is subject to normal operation current. Reference element is not subject to normal operation current. A resistance of detection element is monitored to detect electromigration wearout. The electromigration wearout detection monitoring circuit may be configured to perform: periodically measuring resistance of detection element, calculating resistance change of detection element over a predetermined time period, comparing resistance change of detection element calculated to a predetermined safety threshold, and take mitigation actions when resistance change of detection element exceeds predetermined safety threshold. The mitigation actions may include switching to a redundant circuit of the integrated circuit, shutting down the integrated circuit, and sending a signal to initiate a service call.

Abstract: An inverter circuit for reducing runaway current due to applied voltage stress and temperature conditions comprises: first and second field effect transistor (FET) devices of opposite device polarities for driving a connected second stage device having a connected 2nd stage first and second FET devices, each 2nd stage device having a respective input gate terminal. The first FET and second FET devices have a respective output drive terminal, a first conductive structure connects the first FET output drive terminal to the input gate terminal of each the first and second connected FET device and further connects the first FET output drive terminal to the second FET output drive terminal through a ballasting resistor device. A second separate conductive structure connects the second FET output drive terminal to the input gate terminals and includes a path further connecting the second FET output drive terminal to the first FET output drive terminal through the ballasting resistor device.