Patents by Inventor Solomon I. Beilin

Solomon I. Beilin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6866741
    Abstract: A method for joining large area semiconductor substrates, a liquid thermoset polymer. Two large area substrates, such as wafers or circuit boards (e.g., rigid or flexible), can be joined together by dispensing a liquid polymer inwardly from the edges of the semiconductor substrates. The substrates can then be pressed together so that the liquid thermoset flows in an outwardly direction ward the edges of the semiconductor substrates. Conducting surfaces on the first and second substrates may contact each other after pressing the liquid thermoset polymer. The liquid thermoset polymer in the formed structure may then be cured to a hardened state. The liquid thermoset polymer preferable has a low viscosity, low levels of ionic contaminants, good adhesion to the substrates, low moisture absorbing properties and favorable thermal expansion properties.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: March 15, 2005
    Assignee: Fujitsu Limited
    Inventors: Albert W. Chan, Michael G. Lee, Mark Thomas McCormack, Solomon I. Beilin
  • Patent number: 6845184
    Abstract: Opto-electrical systems having electrical and optical interconnections formed in thin layers are disclosed. In one set of preferred embodiments, optical signals are conveyed between layers by respective vertical optical couplers disposed on the layers. In other preferred embodiments, optical signals are conveyed by stack optical waveguide coupling means. Yet other preferred embodiments have electrical via means formed in one or more layers to covey electrical signals between two or more layers.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: January 18, 2005
    Assignee: Fujitsu Limited
    Inventors: Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William Chou, Solomon I. Beilin, Wen-chou Vincent Wang, James J. Roman, Thomas J. Massingill
  • Patent number: 6785447
    Abstract: An optoreflective structure for reflecting an optical signal following a path defined by an optical waveguide comprising a first cladding layer having a first planar cladding surface; a waveguide disposed on the first cladding layer; and a second cladding layer disposed on the waveguide and having a second planar cladding surface. The first cladding layer, the second cladding layer and the waveguide terminate in a generally dove-tailed structure having a beveled planar surface. An optoreflector is disposed on the beveled planar surface for a changing direction of an optical signal passing through the waveguide. Methods of producing the optoreflective structure are disclosed.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: August 31, 2004
    Assignee: Fujitsu Limited
    Inventors: Tetsuzo Yoshimura, Yasuhito Takahashi, James Roman, Solomon I. Beilin, Wen-chou Vincent Wang, Masaaki Inao
  • Patent number: 6733685
    Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: May 11, 2004
    Assignee: Fujitsu Limited
    Inventors: Solomon I. Beilin, Michael G. Lee, William T. Chou, Larry Louis Moresco, Wen-chou Vincent Wang
  • Patent number: 6706546
    Abstract: A method of constructing an electronic circuit assembly comprising forming at least one electrode on a substrate; forming a layer of undercladding material upon the substrate and over the electrode; and forming a wave guide core layer on the layer of cladding material. The wave guide layer is patterned to produce at least one optical wave guide and exposed undercladding material. The method of constructing further includes forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide; forming at least one via aperture through the overcladding material and the undercladding material; and disposing a conductive material in the via aperture to produce an electronic circuit assembly.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: March 16, 2004
    Assignee: Fujitsu Limited
    Inventors: Tetsuzo Yoshimura, Yashuhito Takahashi, Kiyoshi Kuwabara, Solomon I. Beilin, Michael Peters, Wen-Chou Vincent Wang, Masaaki Inao
  • Patent number: 6690845
    Abstract: Three-dimensional opto-electronic modules having a plurality of opto-electronic (O/E) layers, with optical signals being routed between O/E layers within one or more three-dimensional volumes, are disclosed. In preferred embodiments, the O/E layers are disposed over and above one another with at least one of their edges aligned to one another. At least two of the O/E layers have waveguides with ends near the aligned edges. A plurality of Zconnector arrays are disposed between the O/E layers and within the three-dimensional volumes to provide a plurality of Zdirection waveguides. A first vertical optical coupler couples light from one waveguide in one O/E layer to a Z-direction waveguide, and a second vertical optical coupler couples the light from the Z-direction waveguide to a second waveguide in a second O/E layer. In further preferred embodiments, segments of the Z-connector arrays are held by a holding unit.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: February 10, 2004
    Assignee: Fujitsu Limited
    Inventors: Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William Chou, Solomon I. Beilin, Wen-chou Vincent Wang, James J. Roman, Thomas J. Massingill
  • Patent number: 6684007
    Abstract: An optical apparatus including an optical substrate having an embedded waveguide and an optical device adapted to receive light transmitted from an end of the waveguide. The optical apparatus includes a coupling structure for coupling the optical device to the substrate. The coupling structure has a thin metallic layer with an aperture. At least a portion of the optical device is disposed in the aperture. A method for making an optical apparatus comprising forming an optical substrate having a waveguide embedded therein; depositing a metal layer over an end of the waveguide; and depositing a polymeric layer over the metal layer. An aperture is formed in the metal layer and in the polymeric layer by removing a portion of the metal layer and a portion of the polymeric layer disposed over the end of the waveguide.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: January 27, 2004
    Assignee: Fujitsu Limited
    Inventors: Tetsuzo Yoshimura, Yasuhito Takahashi, James Roman, Mark Thomas McCormack, Solomon I. Beilin, Wen-chou Vincent Wang, Masaaki Inao
  • Patent number: 6611635
    Abstract: Disclosed is device and/or material integration into thin opto-electronic layers, which increase room for chip-mounting, and reduce the total system cost by eliminating the difficulty of optical alignment between opto-electronic devices and optical waveguides. Opto-electronic devices are integrated with optical waveguides in ultra thin polymer layers on the order of 1 &mgr;m to 250 &mgr;m in thickness.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: August 26, 2003
    Assignee: Fujitsu Limited
    Inventors: Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William Chou, Solomon I. Beilin, Wen-chou Vincent Wang, James J. Roman, Thomas J. Massingill
  • Patent number: 6579474
    Abstract: A conductive composition, and articles and methods using the conductive composition are disclosed.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: June 17, 2003
    Assignee: Fujitsu Limited
    Inventors: Mark Thomas McCormack, Hunt Hang Jiang, Solomon I. Beilin, Albert Wong Chan, Yasuhito Takahashi
  • Patent number: 6572780
    Abstract: Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: June 3, 2003
    Assignee: Fujitsu Limited
    Inventors: Mark Thomas McCormack, James Roman, Lei Zhang, Solomon I. Beilin
  • Patent number: 6544430
    Abstract: Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure. Plasma may be used to treat a surface of the release layer or the dielectric film to produce a plasma-treated surface to lower the peel strength of any film or layer bound to the plasma-treated surface.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: April 8, 2003
    Assignee: Fujitsu Limited
    Inventors: Mark Thomas McCormack, James Roman, Lei Zhang, Solomon I. Beilin
  • Patent number: 6509529
    Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: January 21, 2003
    Assignee: Kulicke & Soffa Holdings, Inc.
    Inventors: Sundar Kamath, David Chazan, Jan I. Strandberg, Solomon I. Beilin
  • Publication number: 20020117256
    Abstract: Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure.
    Type: Application
    Filed: May 31, 2001
    Publication date: August 29, 2002
    Inventors: Mark Thomas McCormack, James Roman, Lei Zhang, Solomon I. Beilin
  • Publication number: 20020106522
    Abstract: Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure. Plasma may be used to treat a surface of the release layer or the dielectric film to produce a plasma-treated surface to lower the peel strength of any film or layer bound to the plasma-treated surface.
    Type: Application
    Filed: May 31, 2001
    Publication date: August 8, 2002
    Inventors: Mark Thomas McCormack, James Roman, Lei Zhang, Solomon I. Beilin
  • Publication number: 20020097962
    Abstract: An optoreflective structure for reflecting an optical signal following a path defined by an optical waveguide comprising a first cladding layer having a first planar cladding surface; a waveguide disposed on the first cladding layer; and a second cladding layer disposed on the waveduide and having a second planar cladding surface. The first cladding layer, the second cladding layer and the waveguide terminate in a generally dove-tailed structure having a beveled planar surface. An optoreflector is disposed on the beveled planar surface for a changing direction of an optical signal passing through the waveguide. A method for producing an optoreflective structure comprising providing a substrate supporting a first cladding layer having a first planar cladding surface; disposing a waveguide material on the first cladding layer; and forming on the waveguide material a second cladding layer having a second planar cladding surface.
    Type: Application
    Filed: January 22, 2001
    Publication date: July 25, 2002
    Inventors: Tetsuzo Yoshimura, Yasuhito Takahashi, James Roman, Solomon I. Beilin, Wen-chou Vincent Wang, Masaaki Inao
  • Publication number: 20020088540
    Abstract: A method for joining large area semiconductor substrates, a liquid thermoset polymer. Two large area substrates, such as wafers or circuit boards (e.g., rigid or flexible), can be joined together by dispensing a liquid polymer inwardly from the edges of the semiconductor substrates. The substrates can then be pressed together so that the liquid thermoset flows in an outwardly direction ward the edges of the semiconductor substrates. Conducting surfaces on the first and second substrates may contact each other after pressing the liquid thermoset polymer. The liquid thermoset polymer in the formed structure may then be cured to a hardened state. The liquid thermoset polymer preferable has a low viscosity, low levels of ionic contaminants, good adhesion to the substrates, low moisture absorbing properties and favorable thermal expansion properties.
    Type: Application
    Filed: January 8, 2001
    Publication date: July 11, 2002
    Inventors: Albert W. Chan, Michael G. Lee, Mark Thomas McCormack, Solomon I. Beilin
  • Publication number: 20020039464
    Abstract: A method of constructing an electronic circuit assembly comprising forming at least one electrode on a substrate; forming a layer of undercladding material upon the substrate and over the electrode; and forming a wave guide core layer on the layer of cladding material. The wave guide layer is patterned to produce at least one optical wave guide and exposed undercladding material. The method of constructing further includes forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide; forming at least one via aperture through the overcladding material and the undercladding material; and disposing a conductive material in the via aperture to produce an electronic circuit assembly.
    Type: Application
    Filed: January 8, 2001
    Publication date: April 4, 2002
    Inventors: Tetsuzo Yoshimura, Yasuhito Takahashi, Kiyoshi Kuwabara, Solomon I. Beilin, Michael Peters, Wen-chou Vincent Wang, Masaaki Inao
  • Publication number: 20020028045
    Abstract: An optical apparatus including an optical substrate having an embedded waveguide and an optical device adapted to receive light transmitted from an end of the waveguide. The optical apparatus includes a coupling structure for coupling the optical device to the substrate. The coupling structure has a thin metallic layer with an aperture. At least a portion of the optical device is disposed in the aperture. A method for making an optical apparatus comprising forming an optical substrate having a waveguide embedded therein; depositing a metal layer over an end of the waveguide; and depositing a polymeric layer over the metal layer. An aperture is formed in the metal layer and in the polymeric layer by removing a portion of the metal layer and a portion of the polymeric layer disposed over the end of the waveguide.
    Type: Application
    Filed: May 9, 2001
    Publication date: March 7, 2002
    Inventors: Tetsuzo Yoshimura, Yasuhito Takahashi, James Roman, Mark Thomas McCormack, Solomon I. Beilin, Wen-chou Vincent Wang, Masaaki Inao
  • Publication number: 20020011353
    Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.
    Type: Application
    Filed: September 20, 2001
    Publication date: January 31, 2002
    Inventors: Sundar Kamath, David Chazan, Jan I. Strandberg, Solomon I. Beilin
  • Patent number: 6343171
    Abstract: Opto-electrical systems having electrical and optical interconnections formed in thin layers with thin-film active devices are disclosed. In one embodiment, optical connections are made between the edge of one substrate and the surface of another substrate with the use of photorefractive materials. In another embodiment, the optical connection is made by separating a optical film from the first substrate and coupling the first substrate and the optical film to separate receptacles located on the second substrate. Film optical link modules employing aspects of the invention are also disclosed.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: January 29, 2002
    Assignee: Fujitsu Limited
    Inventors: Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William Chou, Solomon I. Beilin, Wen-chou Vincent Wang, James J. Roman, Thomas J. Massingill