Patents by Inventor Somchai Nondhasitthichai

Somchai Nondhasitthichai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10515878
    Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: December 24, 2019
    Assignee: Utac Headquarters PTE Ltd.
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Woraya Benjasukul
  • Patent number: 10204850
    Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: February 12, 2019
    Assignee: UTAC Headquarters PTE, Ltd.
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Woraya Benjavasukul
  • Patent number: 9947605
    Abstract: A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: April 17, 2018
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 9899208
    Abstract: A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: February 20, 2018
    Assignee: UTAC THAI LIMITED
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
  • Patent number: 9818676
    Abstract: A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: November 14, 2017
    Assignee: UTAC THAI LIMITED
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 9773722
    Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: September 26, 2017
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Woraya Benjavasukul
  • Patent number: 9761435
    Abstract: A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: September 12, 2017
    Assignee: UTAC THAI LIMITED
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 9741642
    Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: August 22, 2017
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Woraya Benjasukul
  • Patent number: 9711343
    Abstract: A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: July 18, 2017
    Assignee: UTAC THAI LIMITED
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
  • Publication number: 20160240460
    Abstract: A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.
    Type: Application
    Filed: April 26, 2016
    Publication date: August 18, 2016
    Applicant: UTAC Thai Limited
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 9349679
    Abstract: A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: May 24, 2016
    Assignee: UTAC THAI LIMITED
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 9196470
    Abstract: A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: November 24, 2015
    Assignee: UTAC THAI LIMITED
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
  • Patent number: 9099294
    Abstract: A process for forming an optical package comprises at least partially encasing a first leadframe strip in a first mold compound thereby forming a molded leadframe strip, mounting at least one optical semiconductor device on the molded leadframe strip, at least partially encasing the molded leadframe strip, and singulating the molded leadframe strip to form discrete packages for optical applications. An apparatus for forming an optical package comprises means for at least partially encasing a first leadframe strip in a first mold compound thereby forming a molded leadframe strip, means for mounting at least one optical semiconductor device on the at least one molded leadframe strip, means for at least partially encasing the molded leadframe strip, and means for singulating the molded leadframe strip to form discrete and grid array packages.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: August 4, 2015
    Assignee: UTAC Thai Limited
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
  • Patent number: 9099317
    Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: August 4, 2015
    Assignee: UTAC Thai Limited
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
  • Patent number: 9093486
    Abstract: A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 28, 2015
    Assignee: UTAC Thai Limited
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
  • Patent number: 9082607
    Abstract: A process for forming an optical package comprises at least partially encasing a first leadframe strip in a first mold compound thereby forming a molded leadframe strip, mounting at least one optical semiconductor device on the molded leadframe strip, at least partially encasing the molded leadframe strip, and singulating the molded leadframe strip to form discrete packages for optical applications. An apparatus for forming an optical package comprises means for at least partially encasing a first leadframe strip in a first mold compound thereby forming a molded leadframe strip, means for mounting at least one optical semiconductor device on the at least one molded leadframe strip, means for at least partially encasing the molded leadframe strip, and means for singulating the molded leadframe strip to form discrete and grid array packages.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: July 14, 2015
    Assignee: UTAC THAI LIMITED
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
  • Patent number: 8704381
    Abstract: A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: April 22, 2014
    Assignee: UTAC Thai Limited
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
  • Patent number: 8685794
    Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 1, 2014
    Assignee: UTAC Thai Limited
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Kasemsan Kongthaworn, Vorajit Suwannaset
  • Patent number: 8652879
    Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: February 18, 2014
    Assignee: UTAC Thai Limited
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Kasemsan Kongthaworn, Vorajit Suwannaset
  • Publication number: 20140015117
    Abstract: A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package.
    Type: Application
    Filed: August 19, 2013
    Publication date: January 16, 2014
    Applicant: UTAC Thai Limited
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul