Patents by Inventor Sommawan KHUMPUANG

Sommawan KHUMPUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10478867
    Abstract: A treatment liquid supply device and a wet treatment device with which an extremely small quantity of the treatment liquid can be accurately supplied, as a method for supplying a treatment liquid to an extremely small wafer of half inch size, including: a syringe that sucks and discharges the treatment liquid; a treatment liquid bottle that is filled with the treatment liquid; a suction hose that has one end connected to the treatment liquid bottle and the other end connected to the syringe, and sucks the treatment liquid inside the treatment liquid bottle to the syringe; a supply hose that has one end connected to an intermediate section of the suction hose and serves to supply, to the surface of the wafer, the treatment liquid discharged by the syringe; and a three-way solenoid valve that controls opening/closing of each of the suction and supply hoses.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: November 19, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Sommawan Khumpuang, Akio Kobayashi, Takeshi Umino, Sonoko Matsuda
  • Patent number: 10431446
    Abstract: A wafer cleaner and a method therefor that efficiently cleans a wafer with a little amount of a cleaning liquid and efficiently performs a heating wet cleaning processing. The present invention includes a stage where a wafer is placed, a rotary driving unit that rotates the stage in a circumferential direction, a liquid discharge nozzle disposed facing the wafer placed on the stage and supplies a cleaning liquid on the wafer placed on the stage, and a control unit that causes the liquid discharge nozzle to supply a space between the wafer placed on the stage and the liquid discharge nozzle with a predetermined amount of the cleaning liquid to fill the space. The present invention also includes a lamp disposed on a position facing the wafer placed on the stage to heat at least an interface portion of the wafer and a cleaning liquid.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: October 1, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Sommawan Khumpuang, Shinichi Ikeda, Akihiro Goto, Hiroshi Amano
  • Patent number: 10304675
    Abstract: A semiconductor manufacturing system has a series of steps, from manufacturing of a semiconductor on a wafer until packaging, that can be easily linked. A semiconductor chip manufacturing device manufactures a semiconductor chip, and a semiconductor packaging device packages the semiconductor chip by attaching the semiconductor chip to a package substrate which is larger than the wafer. The semiconductor chip manufacturing device includes a PLAD system for loading the wafer into and out of the semiconductor chip manufacturing device through a shuttle which is capable of housing the wafer. The semiconductor packaging device includes a PLAD system capable of loading the package substrate into and out of the semiconductor packaging device through a shuttle which is capable of housing the package substrate. The shuttles have container bodies of a same shape.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 28, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Michihiro Inoue, Shiro Hara, Fumito Imura, Arami Saruwatari, Sommawan Khumpuang
  • Patent number: 10286426
    Abstract: A columnar laminar flow generation device includes: a placement part on which to place a processing target; a gas blow-out part having an opening; and a gas suction path; wherein the placement part is positioned in a space whose outer periphery surface is constituted by extending the interior wall of the opening in the direction vertical to the opening; the opening has, in its interior wall, a gas blow-out port through which a gas is blown out in one direction vertical to the opening; and the gas suction path is formed in such a way that it suctions the gas in the direction opposite to the one in which the gas is blown out. The columnar laminar generation device is capable of generating columnar laminar flows.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: May 14, 2019
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, LITHO TECH JAPAN CORPORATION, ORIENTAL MOTOR CO., LTD.
    Inventors: Shuuji Okuda, Sommawan Khumpuang, Shiro Hara, Sho Takeuchi, Yoshihisa Sensu, Takahiro Ito
  • Patent number: 10186489
    Abstract: To provide a crystal orientation mark which can be formed easily and inexpensively, and which enables to perform high precision alignment and allows information other than crystal orientation to be included, even for a small diameter process substrate. A crystal orientation mark is drawn on the surface of the process substrate. The crystal orientation mark includes a marking region for crystal orientation detection, and a marking region for information. The marking region for crystal orientation detection is provided at two locations in an outer edge portion of the process substrate to be used for the alignment of the process substrate. The marking region for information is provided on a straight-line region connecting the marking regions for crystal orientation detection at the two locations, and includes a pattern for demonstrating predetermined information relating to the process substrate.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: January 22, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Sommawan Khumpuang, Shinichi Ikeda
  • Patent number: 10163819
    Abstract: A method for manufacturing a surface-mount type package whose face parallel with the semiconductor chip surface has a circular cross-section, is characterized by including at least the following steps in this order: a first step in which a semiconductor chip is bonded onto a circular support substrate; a second step in which the semiconductor chip is sealed with resin; a third step in which the resin covering the pads of the semiconductor chip is removed; a fourth step in which a rewiring layer is formed; and a fifth step in which bumps are formed. The method can provide a surface-mount type package for semiconductor chips which is resistant to failures caused by thermal stress.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 25, 2018
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Sommawan Khumpuang, Fumito Imura, Michihiro Inoue, Arami Saruwatari
  • Patent number: 10163674
    Abstract: An object of the present invention is to provide a circular support substrate that allows for positioning based solely on its outer periphery shape. As a means for solving the problems, a circular support substrate is provided that has at least three chords along its circumference, wherein the chords are provided at positions where they do not run linearly symmetrical to the straight line passing through the center axis of the circular support substrate.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 25, 2018
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Sommawan Khumpuang, Fumito Imura, Michihiro Inoue, Arami Saruwatari
  • Publication number: 20180025994
    Abstract: An object of the present invention is to provide a surface-mount type package for semiconductor chips which is resistant to failures caused by thermal stress. As a means for achieving the object, a method for manufacturing a surface-mount type package whose face parallel with the semiconductor chip surface has a circular cross-section, is provided, wherein such method is characterized in that it comprises at least the following steps in this order. A first step in which a semiconductor chip is bonded onto a circular support substrate. A second step in which the semiconductor chip is sealed with resin. A third step in which the resin covering the pads of the semiconductor chip is removed. A fourth step in which a rewiring layer is formed. A fifth step in which bumps are formed.
    Type: Application
    Filed: November 24, 2015
    Publication date: January 25, 2018
    Inventors: Shiro HARA, Sommawan KHUMPUANG, Fumito IMURA, Michihiro INOUE, Arami SARUWATARI
  • Publication number: 20180001354
    Abstract: A treatment liquid supply device and a wet treatment device with which an extremely small quantity of the treatment liquid can be accurately supplied, as a method for supplying a treatment liquid to an extremely small wafer of half inch size, including: a syringe that sucks and discharges the treatment liquid; a treatment liquid bottle that is filled with the treatment liquid; a suction hose that has one end connected to the treatment liquid bottle and the other end connected to the syringe, and sucks the treatment liquid inside the treatment liquid bottle to the syringe; a supply hose that has one end connected to an intermediate section of the suction hose and serves to supply, to the surface of the wafer, the treatment liquid discharged by the syringe; and a three-way solenoid valve that controls opening/closing of each of the suction and supply hoses.
    Type: Application
    Filed: December 2, 2015
    Publication date: January 4, 2018
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro HARA, Sommawan KHUMPUANG, Akio KOBAYASHI, Takeshi UMINO, Sonoko MATSUDA
  • Publication number: 20170352570
    Abstract: An object of the present invention is to provide a circular support substrate that allows for positioning based solely on its outer periphery shape. As a means for solving the problems, a circular support substrate is provided that has at least three chords along its circumference, wherein the chords are provided at positions where they do not run linearly symmetrical to the straight line passing through the center axis of the circular support substrate.
    Type: Application
    Filed: November 24, 2015
    Publication date: December 7, 2017
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Shiro HARA, Sommawan KHUMPUANG, Fumito IMURA, Michihiro INOUE, Arami SARUWATARI
  • Publication number: 20170330741
    Abstract: A semiconductor manufacturing system has a series of steps, from manufacturing of a semiconductor on a wafer until packaging, that can be easily linked. A semiconductor chip manufacturing device manufactures a semiconductor chip, and a semiconductor packaging device packages the semiconductor chip by attaching the semiconductor chip to a package substrate which is larger than the wafer. The semiconductor chip manufacturing device includes a PLAD system for loading the wafer into and out of the semiconductor chip manufacturing device through a shuttle which is capable of housing the wafer. The semiconductor packaging device includes a PLAD system capable of loading the package substrate into and out of the semiconductor packaging device through a shuttle which is capable of housing the package substrate. The shuttles have container bodies of a same shape.
    Type: Application
    Filed: November 16, 2015
    Publication date: November 16, 2017
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Michihiro INOUE, Shiro HARA, Fumito IMURA, Arami SARUWATARI, Sommawan KHUMPUANG
  • Patent number: 9777375
    Abstract: Provide a converging mirror-based furnace for heating a target by way of reflecting from a reflecting mirror unit the light emitted from a light source and then irradiating a target with the reflected light, wherein said target-heating converging-light furnace is such that: the reflecting mirror unit comprises a primary reflecting mirror and secondary reflecting mirror; the light emitted from the light source is reflected sequentially by the primary reflecting mirror and secondary reflecting mirror and then irradiated onto the target; and the light reflected by the secondary reflecting mirror and irradiated onto the target surface is not perpendicular to the target surface. Based on the above, a system that uses converged infrared light to provide heating can be made smaller while keeping its heating performance intact, even when the system uses a revolving ellipsoid.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: October 3, 2017
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shinichi Ikeda, Shiro Hara, Takanori Mikahara, Hitoshi Habuka, Sommawan Khumpuang
  • Publication number: 20170098557
    Abstract: To provide a plasma device that all functions required for a plasma etching process are incorporated into a narrow space of a minimal fabrication manufacturing device. A plasma processing chamber for performing the plasma etching process on a semiconductor wafer is provided, and a micro-plasma supply section and a lower electrode that superimposes RF on supplied micro-plasma are provided in the plasma processing chamber. A wafer support device that supports the semiconductor wafer supports the semiconductor wafer in the plasma processing chamber during the etching process. The wafer support device is coupled to and supported by a drive section that is arranged outside the plasma processing chamber. The drive section makes the wafer support device repetitively move scanningly in the plasma processing chamber in parallel with a wafer processing surface during the etching process.
    Type: Application
    Filed: March 10, 2015
    Publication date: April 6, 2017
    Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, DESIGN NETWORK CO., LTD.
    Inventors: Yoshiki SHIMIZU, Shiro HARA, Hiroyuki TANAKA, Shizuka NAKANO, Hisato OGISO, Sommawan KHUMPUANG, Shinji FUTAGAWA, Hideaki YOSHIOKA, Takahiro FUKUDA, Yoshinori UCHIYAMA
  • Publication number: 20170072438
    Abstract: A columnar laminar flow generation device includes: a placement part on which to place a processing target; a gas blow-out part having an opening; and a gas suction path; wherein the placement part is positioned in a space whose outer periphery surface is constituted by extending the interior wall of the opening in the direction vertical to the opening; the opening has, in its interior wall, a gas blow-out port through which a gas is blown out in one direction vertical to the opening; and the gas suction path is formed in such a way that it suctions the gas in the direction opposite to the one in which the gas is blown out. The columnar laminar generation device is capable of generating columnar laminar flows.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 16, 2017
    Inventors: Shuuji OKUDA, Sommawan KHUMPUANG, Shiro HARA, Sho TAKEUCHI, Yoshihisa SENSU, Takahiro ITO
  • Patent number: 9513567
    Abstract: To provide a mask aligner that can appropriately manage very small-quantity production and multiproduct production. The present invention is a mask aligner 1 that exposes a wafer W in a predetermined size through a mask M, and has a configuration that includes: a conveying device 5 for conveying the wafer W and the mask M; an exposure stage 3f on which the wafer W conveyed by the conveying device 5 is installed; a mask holder 3b that is mounted to face the exposure stage 3f and on which the mask M conveyed by the conveying device 5 is installed; and an LED light source 8c mounted to face the exposure stage 3f via the mask holder 3b.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: December 6, 2016
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Shiro Hara, Sommawan Khumpuang, Yoshiki Inuzuka, Yasuaki Yokoyama
  • Publication number: 20160293401
    Abstract: A wafer cleaner and a method therefor that efficiently cleans a wafer with a little amount of a cleaning liquid and efficiently performs a heating wet cleaning processing. The present invention includes a stage where a wafer is placed, a rotary driving unit that rotates the stage in a circumferential direction, a liquid discharge nozzle disposed facing the wafer placed on the stage and supplies a cleaning liquid on the wafer placed on the stage, and a control unit that causes the liquid discharge nozzle to supply a space between the wafer placed on the stage and the liquid discharge nozzle with a predetermined amount of the cleaning liquid to fill the space. The present invention also includes a lamp disposed on a position facing the wafer placed on the stage to heat at least an interface portion of the wafer and a cleaning liquid.
    Type: Application
    Filed: December 1, 2014
    Publication date: October 6, 2016
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro HARA, Sommawan KHUMPUANG, Shinichi IKEDA, Akihiro GOTO, Hiroshi AMANO
  • Publication number: 20160211218
    Abstract: To provide a crystal orientation mark which can be formed easily and inexpensively, and which enables to perform high precision alignment and allows information other than crystal orientation to be included, even for a small diameter process substrate. A crystal orientation mark is drawn on the surface of the process substrate. The crystal orientation mark includes a marking region for crystal orientation detection, and a marking region for information. The marking region for crystal orientation detection is provided at two locations in an outer edge portion of the process substrate to be used for the alignment of the process substrate. The marking region for information is provided on a straight-line region connecting the marking regions for crystal orientation detection at the two locations, and includes a pattern for demonstrating predetermined information relating to the process substrate.
    Type: Application
    Filed: July 24, 2014
    Publication date: July 21, 2016
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro HARA, Sommawan KHUMPUANG, Shinichi IKEDA
  • Patent number: 9123795
    Abstract: A method of manufacturing semiconductor wafers which facilitates formation of orientation flat lines and allows beveling work without problems. The method of manufacturing semiconductor wafers includes steps wherein a plurality of small-diameter wafers is cut out from a large-diameter semiconductor wafer, the method including: a marking step of forming straight groove-like orientation flat lines by a laser beam so as to cross the respective small-diameter wafers in each row in the large-diameter semiconductor wafer, wherein cutout positions of the small-diameter wafers are aligned in rows in a specific direction, collectively for each of the rows; and a cutting step of cutting out the small-diameter wafers separately from the large-diameter semiconductor wafer, by a laser beam, after the marking step, in such a way that the orientation flat lines are located at required positions in the small-diameter wafers to be obtained.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 1, 2015
    Assignees: FUJIKOSHI MACHINERY CORP., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yoshio Nakamura, Daizo Ichikawa, Haruo Sumizawa, Shiro Hara, Sommawan Khumpuang, Shinichi Ikeda
  • Patent number: 9017146
    Abstract: The wafer polishing apparatus comprises a polishing plate, a polishing head capable of holding a wafer, and a slurry supplying section. The polishing plate includes: a plurality of concentric polishing zones, each of which has a prescribed width for polishing the wafer and on each of which a polishing cloth is adhered; and a groove for discharging slurry being formed between the polishing zones. A head cleaning section, which cleans the polishing head, or a wafer cleaning section, which cleans the polished wafer, is provided to a center part of the polishing plate and located on the inner side of the innermost polishing zone.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: April 28, 2015
    Assignees: Fujikoshi Machinery Corp., National Institute of Advanced Industrial Science and Technology
    Inventors: Yoshio Nakamura, Yoshio Otsuka, Takashi Okubo, Kazutaka Shibuya, Takayuki Fuse, Shiro Hara, Sommawan Khumpuang, Shinichi Ikeda
  • Publication number: 20150050602
    Abstract: An optimal development method and an apparatus of a resist formed on a half-inch size wafer. The development method is a development method of a resist formed on a wafer with a wafer size for manufacturing a number of minimized units of semiconductor devices. The method includes a first step, a second step, a third step, and a fourth step. The first step drops developer until a thickness of developer becomes maximum on the wafer whose rotation is stopped. The second step performs development while rotating the wafer. The third step supplies the developer about a half of the amount of developer of the first step on the wafer whose rotation is stopped. The fourth step performs development at a development period longer than the second step while rotating the wafer.
    Type: Application
    Filed: October 3, 2012
    Publication date: February 19, 2015
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Sommawan Khumpuang, Shiro Hara