Patents by Inventor Sommawan KHUMPUANG

Sommawan KHUMPUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160293401
    Abstract: A wafer cleaner and a method therefor that efficiently cleans a wafer with a little amount of a cleaning liquid and efficiently performs a heating wet cleaning processing. The present invention includes a stage where a wafer is placed, a rotary driving unit that rotates the stage in a circumferential direction, a liquid discharge nozzle disposed facing the wafer placed on the stage and supplies a cleaning liquid on the wafer placed on the stage, and a control unit that causes the liquid discharge nozzle to supply a space between the wafer placed on the stage and the liquid discharge nozzle with a predetermined amount of the cleaning liquid to fill the space. The present invention also includes a lamp disposed on a position facing the wafer placed on the stage to heat at least an interface portion of the wafer and a cleaning liquid.
    Type: Application
    Filed: December 1, 2014
    Publication date: October 6, 2016
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro HARA, Sommawan KHUMPUANG, Shinichi IKEDA, Akihiro GOTO, Hiroshi AMANO
  • Publication number: 20160211218
    Abstract: To provide a crystal orientation mark which can be formed easily and inexpensively, and which enables to perform high precision alignment and allows information other than crystal orientation to be included, even for a small diameter process substrate. A crystal orientation mark is drawn on the surface of the process substrate. The crystal orientation mark includes a marking region for crystal orientation detection, and a marking region for information. The marking region for crystal orientation detection is provided at two locations in an outer edge portion of the process substrate to be used for the alignment of the process substrate. The marking region for information is provided on a straight-line region connecting the marking regions for crystal orientation detection at the two locations, and includes a pattern for demonstrating predetermined information relating to the process substrate.
    Type: Application
    Filed: July 24, 2014
    Publication date: July 21, 2016
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro HARA, Sommawan KHUMPUANG, Shinichi IKEDA
  • Patent number: 9123795
    Abstract: A method of manufacturing semiconductor wafers which facilitates formation of orientation flat lines and allows beveling work without problems. The method of manufacturing semiconductor wafers includes steps wherein a plurality of small-diameter wafers is cut out from a large-diameter semiconductor wafer, the method including: a marking step of forming straight groove-like orientation flat lines by a laser beam so as to cross the respective small-diameter wafers in each row in the large-diameter semiconductor wafer, wherein cutout positions of the small-diameter wafers are aligned in rows in a specific direction, collectively for each of the rows; and a cutting step of cutting out the small-diameter wafers separately from the large-diameter semiconductor wafer, by a laser beam, after the marking step, in such a way that the orientation flat lines are located at required positions in the small-diameter wafers to be obtained.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 1, 2015
    Assignees: FUJIKOSHI MACHINERY CORP., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yoshio Nakamura, Daizo Ichikawa, Haruo Sumizawa, Shiro Hara, Sommawan Khumpuang, Shinichi Ikeda
  • Patent number: 9017146
    Abstract: The wafer polishing apparatus comprises a polishing plate, a polishing head capable of holding a wafer, and a slurry supplying section. The polishing plate includes: a plurality of concentric polishing zones, each of which has a prescribed width for polishing the wafer and on each of which a polishing cloth is adhered; and a groove for discharging slurry being formed between the polishing zones. A head cleaning section, which cleans the polishing head, or a wafer cleaning section, which cleans the polished wafer, is provided to a center part of the polishing plate and located on the inner side of the innermost polishing zone.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: April 28, 2015
    Assignees: Fujikoshi Machinery Corp., National Institute of Advanced Industrial Science and Technology
    Inventors: Yoshio Nakamura, Yoshio Otsuka, Takashi Okubo, Kazutaka Shibuya, Takayuki Fuse, Shiro Hara, Sommawan Khumpuang, Shinichi Ikeda
  • Publication number: 20150050602
    Abstract: An optimal development method and an apparatus of a resist formed on a half-inch size wafer. The development method is a development method of a resist formed on a wafer with a wafer size for manufacturing a number of minimized units of semiconductor devices. The method includes a first step, a second step, a third step, and a fourth step. The first step drops developer until a thickness of developer becomes maximum on the wafer whose rotation is stopped. The second step performs development while rotating the wafer. The third step supplies the developer about a half of the amount of developer of the first step on the wafer whose rotation is stopped. The fourth step performs development at a development period longer than the second step while rotating the wafer.
    Type: Application
    Filed: October 3, 2012
    Publication date: February 19, 2015
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Sommawan Khumpuang, Shiro Hara
  • Publication number: 20140338591
    Abstract: Provide a converging mirror-based furnace for heating a target by way of reflecting from a reflecting mirror unit the light emitted from a light source and then irradiating a target with the reflected light, wherein said target-heating converging-light furnace is such that: the reflecting mirror unit comprises a primary reflecting mirror and secondary reflecting mirror; the light emitted from the light source is reflected sequentially by the primary reflecting mirror and secondary reflecting mirror and then irradiated onto the target; and the light reflected by the secondary reflecting mirror and irradiated onto the target surface is not perpendicular to the target surface. Based on the above, a system that uses converged infrared light to provide heating can be made smaller while keeping its heating performance intact, even when the system uses a revolving ellipsoid.
    Type: Application
    Filed: November 30, 2012
    Publication date: November 20, 2014
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shinichi Ikeda, Shiro Hara, Takanori Mikahara, Hitoshi Habuka, Sommawan Khumpuang
  • Publication number: 20140320840
    Abstract: To provide a mask aligner that can appropriately manage very small-quantity production and multiproduct production. The present invention is a mask aligner 1 that exposes a wafer W in a predetermined size through a mask M, and has a configuration that includes: a conveying device 5 for conveying the wafer W and the mask M; an exposure stage 3f on which the wafer W conveyed by the conveying device 5 is installed; a mask holder 3b that is mounted to face the exposure stage 3f and on which the mask M conveyed by the conveying device 5 is installed; and an LED light source 8c mounted to face the exposure stage 3f via the mask holder 3b.
    Type: Application
    Filed: December 4, 2012
    Publication date: October 30, 2014
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Shiro Hara, Sommawan Khumpuang, Yoshiki Inuzuka, Yasuaki Yokoyama
  • Publication number: 20140154870
    Abstract: A method of manufacturing semiconductor wafers is provided which facilitates formation of orientation flat lines and allows beveling work without problems. The method of manufacturing semiconductor wafers according to the present invention is a method of manufacturing semiconductor wafers, in which a plurality of small-diameter wafers is cut out from a large-diameter semiconductor wafer, the method including: a marking step of forming straight groove-like orientation flat lines by a laser beam so as to cross the respective small-diameter wafers in each row in the large-diameter semiconductor wafer, wherein cutout positions of the small-diameter wafers are aligned in rows in a specific direction, collectively for each of the rows; and a cutting step of cutting out the small-diameter wafers separately from the large-diameter semiconductor wafer by a laser beam after the marking step.
    Type: Application
    Filed: November 22, 2013
    Publication date: June 5, 2014
    Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, Fujikoshi Machinery Corp.
    Inventors: Yoshio NAKAMURA, Daizo ICHIKAWA, Haruo SUMIZAWA, Shiro HARA, Sommawan KHUMPUANG, Shinichi IKEDA
  • Publication number: 20140154958
    Abstract: The wafer polishing apparatus comprises a polishing plate, a polishing head capable of holding a wafer, and a slurry supplying section. The polishing plate includes: a plurality of concentric polishing zones, each of which has a prescribed width for polishing the wafer and on each of which a polishing cloth is adhered; and a groove for discharging slurry being formed between the polishing zones. A head cleaning section, which cleans the polishing head, or a wafer cleaning section, which cleans the polished wafer, is provided to a center part of the polishing plate and located on the inner side of the innermost polishing zone.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 5, 2014
    Applicants: National Institute of Advanced Industrial Science and Technology, Fujikoshi Machinery Corp.
    Inventors: Yoshio NAKAMURA, Yoshio OTSUKA, Takashi OKUBO, Kazutaka SHIBUYA, Takayuki FUSE, Shiro HARA, Sommawan KHUMPUANG, Shinichi IKEDA