Patents by Inventor Somnath Nag
Somnath Nag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10096473Abstract: Described herein are techniques for forming an epitaxial III-V layer on a substrate. In a pre-clean chamber, a native oxygen layer may be replaced with a passivation layer by treating the substrate with a hydrogen plasma (or products of a plasma decomposition). In a deposition chamber, the temperature of the substrate may be elevated to a temperature less than 700° C. While the substrate temperature is elevated, a group V precursor may be flowed into the deposition chamber in order to transform the hydrogen terminated (Si—H) surface of the passivation layer into an Arsenic terminated (Si—As) surface. After the substrate has been cooled, a group III precursor and the group V precursor may be flowed in order to form a nucleation layer. Finally, at an elevated temperature, the group III precursor and group V precursor may be flowed in order to form a bulk III-V layer.Type: GrantFiled: April 7, 2016Date of Patent: October 9, 2018Assignee: AIXTRON SEInventors: Maxim Kelman, Zhongyuan Jia, Somnath Nag, Robert Ditizio
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Patent number: 9869031Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).Type: GrantFiled: April 6, 2015Date of Patent: January 16, 2018Assignee: OB Realty, LLCInventors: George D. Kamian, Somnath Nag, Subramanian Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
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Publication number: 20170294306Abstract: Described herein are techniques for forming an epitaxial III-V layer on a substrate. In a pre-clean chamber, a native oxygen layer may be replaced with a passivation layer by treating the substrate with a hydrogen plasma (or products of a plasma decomposition). In a deposition chamber, the temperature of the substrate may be elevated to a temperature less than 700° C. While the substrate temperature is elevated, a group V precursor may be flowed into the deposition chamber in order to transform the hydrogen terminated (Si—H) surface of the passivation layer into an Arsenic terminated (Si—As) surface. After the substrate has been cooled, a group III precursor and the group V precursor may be flowed in order to form a nucleation layer. Finally, at an elevated temperature, the group III precursor and group V precursor may be flowed in order to form a bulk III-V layer.Type: ApplicationFiled: April 7, 2016Publication date: October 12, 2017Inventors: Maxim Kelman, Zhongyuan Jia, Somnath Nag, Robert Ditizio
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Publication number: 20170141720Abstract: Photovoltaic modules including a plurality of solar cells bonded to a module back sheet are described herein, wherein each solar cell includes a superstrate bonded to a front side of a photovoltaic device to facilitate handling of very thin photovoltaic devices during fabrication of the module. Modules may also include module front sheets and the solar cells may include bottom sheets. The modules may be made of flexible materials, and may be foldable. Fabrication processes include tabbing photovoltaic devices prior to attaching the individual superstrates.Type: ApplicationFiled: October 8, 2015Publication date: May 18, 2017Inventors: Kramadhati V. Ravi, Tirunelveli S. Ravi, Ashish Asthana, Somnath Nag
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Patent number: 9455360Abstract: Methods of fabricating metal wrap through solar cells and modules for thin silicon solar cells, including epitaxial silicon solar cells, are described. These metal wrap through solar cells have a planar back contact geometry for the base and emitter contacts. Fabrication of a metal wrap through solar cell may comprise: providing a photovoltaic device attached at the emitter side of the device to a solar glass by an encapsulant, the device including busbars on the device emitter; forming vias through the device base and emitter, the vias terminating in the busbars; depositing a conformal dielectric film over the surface of the vias and the back surface of the base; removing portions of the conformal dielectric film from the ends of the vias for exposing the busbars and from field areas of the base; and forming separate electrical contacts to the busbars and the field areas on the back surface of the solar cell.Type: GrantFiled: November 7, 2014Date of Patent: September 27, 2016Assignee: Crystal Solar, Inc.Inventors: Ashish Asthana, Tirunelveli S. Ravi, Kramadhati V. Ravi, Somnath Nag
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Publication number: 20160233824Abstract: Photovoltaic modules including a plurality of solar cells bonded to a module back sheet are described herein, wherein each solar cell includes a superstrate bonded to a front side of a photovoltaic device to facilitate handling of very thin photovoltaic devices during fabrication of the module. Modules may also include module front sheets and the solar cells may include bottom sheets. The modules may be made of flexible materials, and may be foldable. Fabrication processes include tabbing photovoltaic devices prior to attaching the individual superstrates.Type: ApplicationFiled: October 8, 2015Publication date: August 11, 2016Inventors: Kramadhati V. Ravi, Tirunelveli S. Ravi, Ashish Asthana, Somnath Nag
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Patent number: 9401276Abstract: An apparatus for forming porous silicon layers on at least two surfaces of a plurality of silicon templates in a batch electrochemical anodic etch process is provided. The apparatus comprises a plurality of edge-sealing template mounts operable to prevent formation of porous silicon at the edges of a plurality of templates. An electrolyte is disposed among the plurality of templates. The apparatus further comprises a power supply operable to switch polarity, change current intensity, and control etching time to produce the porous silicon layers.Type: GrantFiled: July 20, 2012Date of Patent: July 26, 2016Assignee: Solexel, Inc.Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D. Kamian, Jay Ashjaee, Takao Yonehara
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Publication number: 20150315719Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).Type: ApplicationFiled: April 6, 2015Publication date: November 5, 2015Inventors: George D. Kamian, Somnath Nag, Subbu Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
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Publication number: 20150311721Abstract: Systems, methods, and apparatuses are disclosed for remote access, and management of a power grid and their associated loads. At least certain embodiments are configured for provisioning and control of decentralized non-grid connected power sources and corresponding power loads, including DC from photovoltaics (“PVs”) and AC from inverters, to a variety of power loads such as various electrical motors, lights as well as residential or business appliances. Aspects of the techniques described herein further include automated monitoring of various sensors including sensors that measure power, voltage, current, temperature, and humidity of the power sources as well as notification triggers and alarms to a feature phone. Other aspects are further adapted to track and receive payment for electric power from consumers connected with the decentralized non-grid power sources. The control of the power sources and loads can be bi-directional and can be performed using a smartphone that interfaces with a microcontroller.Type: ApplicationFiled: December 9, 2013Publication date: October 29, 2015Inventors: Sanjay UPPAL, Somnath NAG, Irfan Arshad MALIK
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Publication number: 20150299892Abstract: It is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high volume production of photovoltaic (PV) solar cell device architecture. It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon. The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure. Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer.Type: ApplicationFiled: January 5, 2015Publication date: October 22, 2015Inventors: Mehrdad M. Moslehi, Doug Crafts, Subramanian Tamilmani, Karl-Josef Kramer, George D. Kamian, Somnath Nag
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Patent number: 9093323Abstract: Methods here disclosed provide for selectively coating three-dimensional features on a substrate while avoiding liquid coating material wicking into micro cavities on the substrates. The steps include depositing a semiconductor layer on a sacrificial layer formed on a template and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating three-dimensional features on the substrate using a liquid coating step for applying a liquid coating material to a pre-determined surface of the three-dimensional features on the substrate.Type: GrantFiled: July 15, 2013Date of Patent: July 28, 2015Assignee: Solexel, Inc.Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi, Somnath Nag
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Publication number: 20150187966Abstract: Methods of fabricating metal wrap through solar cells and modules for thin silicon solar cells, including epitaxial silicon solar cells, are described. These metal wrap through solar cells have a planar back contact geometry for the base and emitter contacts. Fabrication of a metal wrap through solar cell may comprise: providing a photovoltaic device attached at the emitter side of the device to a solar glass by an encapsulant, the device including busbars on the device emitter; forming vias through the device base and emitter, the vias terminating in the busbars; depositing a conformal dielectric film over the surface of the vias and the back surface of the base; removing portions of the conformal dielectric film from the ends of the vias for exposing the busbars and from field areas of the base; and forming separate electrical contacts to the busbars and the field areas on the back surface of the solar cell.Type: ApplicationFiled: November 7, 2014Publication date: July 2, 2015Inventors: Ashish Asthana, Tirunelveli S. Ravi, Kramadhati V. Ravi, Somnath Nag
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Patent number: 9053957Abstract: A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The reusable template has a three-dimensional (3-D) surface topography comprising a plurality of raised areas comprising a rounded top and separated by a plurality of depressed areas.Type: GrantFiled: May 17, 2013Date of Patent: June 9, 2015Assignee: Solexel, Inc.Inventors: Suketu Parikh, David Dutton, Pawan Kapur, Somnath Nag, Mehrdad M. Moslehi, Karl-Josef Kramer, Nevran Ozguven, Burcu Ucok
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Patent number: 8999058Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).Type: GrantFiled: May 5, 2010Date of Patent: April 7, 2015Assignee: Solexel, Inc.Inventors: George D. Kamian, Somnath Nag, Subbu Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
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Patent number: 8926803Abstract: It is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high volume production of photovoltaic (PV) solar cell device architecture. It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon. The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure. Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer.Type: GrantFiled: January 15, 2010Date of Patent: January 6, 2015Assignee: Solexel, Inc.Inventors: Doug Crafts, Mehrdad Moslehi, Subramanian Tamilmani, Joe Kramer, George D. Kamian, Somnath Nag
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Patent number: 8883552Abstract: Methods of fabricating metal wrap through solar cells and modules for thin silicon solar cells, including epitaxial silicon solar cells, are described. These metal wrap through solar cells have a planar back contact geometry for the base and emitter contacts. Fabrication of a metal wrap through solar cell may comprise: providing a photovoltaic device attached at the emitter side of the device to a solar glass by an encapsulant, the device including busbars on the device emitter; forming vias through the device base and emitter, the vias terminating in the busbars; depositing a conformal dielectric film over the surface of the vias and the back surface of the base; removing portions of the conformal dielectric film from the ends of the vias for exposing the busbars and from field areas of the base; and forming separate electrical contacts to the busbars and the field areas on the back surface of the solar cell.Type: GrantFiled: August 11, 2011Date of Patent: November 11, 2014Assignee: Crystal Solar Inc.Inventors: Ashish Asthana, Tirunelveli S. Ravi, Kramadhati V. Ravi, Somnath Nag
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Publication number: 20140127834Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate.Type: ApplicationFiled: July 15, 2013Publication date: May 8, 2014Applicant: Solexel, Inc.Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi, Somnath Nag
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Publication number: 20130241038Abstract: A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The template has a shape such that the 3-D shape is substantially retained after each substrate release. Prior art reusable templates may have a tendency to change shape after each subsequent reuse; the present disclosure aims to address this and other deficiencies from the prior art, therefore increasing the reuse life of the template.Type: ApplicationFiled: May 17, 2013Publication date: September 19, 2013Applicant: Solexel, Inc.Inventors: Suketu Parikh, David Dutton, Pawan Kapur, Somnath Nag, Mehrdad M. Moslehi, Karl-Josef Kramer, Nevran Ozguven, Burcu Ucok
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Patent number: 8512581Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate.Type: GrantFiled: August 18, 2008Date of Patent: August 20, 2013Assignee: Solexel, Inc.Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi, Somnath Nag
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Publication number: 20130171808Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.Type: ApplicationFiled: July 20, 2012Publication date: July 4, 2013Applicant: SOLEXEL, INC.Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D. Kamian, Jay Ashjaee, Takao Yonehara