Abstract: A method of making and testing a system on chip (SOC) comprises providing an integrated system test (IST) module in each one of a plurality of SOC components. At least one of the SOC components communicates with an external interface and at least one other of the SOC components. The method includes receiving test configuration data, transmitting test result data, and transmitting and receiving application data via the external interface. The method includes using at least one of the IST modules to receive the test configuration data and configure the IST modules to test the plurality of SOC components.

Abstract: A system comprises a printed circuit board (PCB). A system on chip (SOC) mounted on the PCB includes a controller that communicates with an external interface that receives test configuration data, transmits test result data, and transmits and receives application data. At least one chip mounted to the PCB, wherein the SOC comprises an SOC component that includes an integrated system test (IST) module. At least one chip comprises a chip component that includes an integrated system test (IST) module. At least one of the SOC component and the chip component, communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing at least one of the SOC component and the chip component.

Abstract: A hard disk drive system includes an external interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. The hard disk drive system includes a system on chip (SOC) that includes a controller and a read/write channel that communicates with the controller and that includes an integrated system test (IST) module that communicates with the external interface. A memory module communicates with the SOC and includes memory and an IST module. The hard disk drive system includes a spindle/voice coil motor driver module that includes an IST module. At least one of the IST modules is a master IST module that receives the test configuration data and that configures the IST modules for testing at least one of the controller, the read/write channel, and the memory module.

Abstract: A system on chip (SOC), comprises an external interface that receives test configuration data, transmits test result data, and that transmits and receives application data. A plurality of SOC components, each including an integrated system test (IST) module, wherein at least one of the SOC components includes a controller that communicates with the external interface. At least one of the plurality of SOC components communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing the plurality of SOC components.

Abstract: A hard disk drive system comprises N hard disk drive means for performing hard disk drive functions and is connected in a daisy chain, wherein N is greater than one. The system includes integrated system test (IST) means for testing and that is integrated with a first one of the N hard disk drive means and includes pattern generating means for generating test pattern data and pattern monitoring means for receiving a returned test pattern. The pattern generating means generates test pattern data that is routed from the first one of the N hard disk drive means serially through the remaining ones of the N hard disk drive means and back to the first one of the N hard disk drive means. The pattern monitoring means generates test result data based on returned test data returned to the first one of the N hard disk drive means.

Abstract: A memory storage system includes a line cache including a plurality of pages. A first central processing unit (CPU) accesses data stored in the pages of the line cache. A first memory device stores data that is loaded into the line cache when a miss occurs. After an initial miss, the line cache prevents additional misses as long as the first CPU is addressing sequential memory locations of the first memory device. When the miss occurs, n pages of the line cache are loaded with data from sequential locations in the first memory device, wherein n is greater than one. When the CPU requests data from an mth page of the n pages in the line cache, wherein m is greater than one and less than or equal to n, the line cache loads p additional pages with data from sequential locations in the first memory device.

Abstract: An integrated circuit controls the low level, electromechanical functionality of a computer mass storage device, such as a magnetic disk drive incorporating a spindle motor for rotatably controlling a disk and an actuator for positioning at least one read/write head with respect to the disk, to read or write encoded data configured in information data sectors and to sense encoded data of servo data sectors. A servo subsystem is coupled to an output of the read/write head for detecting the servo data sectors and providing a control signal in response thereto. An analog-to-digital subsystem is also coupled to an output of the read/write head and is operative in response to the servo subsystem control signal for converting the encoded data of the servo data sectors to digital transducer position information representative of a position of the read/write head with respect to the data tracks.

Abstract: A burst magnitude comparator and an instruction sequencer are employed in a servo system controller to rapidly determine position correction information for moving a transducer head over the center line of a track recorded on a disk in a mass storage disk drive. The burst magnitude comparator selects at least two burst signals derived from bursts recorded at predetermined locations relative to the center line from which to derive a correction control signal, based on a predetermined relationship of the burst signals, and supplies the selected burst signals in a predetermined order to facilitate calculation of the correction signal by a data processor used with the servo system controller. An instruction sequencer controls a sequence of converting the analog burst signals from the head to digital burst signals without intervention or control from the data processor.

Abstract: A servo system controller for a disk drive device which includes a rotating mass storage disk incorporates a timing error determining circuit for determining rotational speed variations in the disk from information contained in a servo field recorded in a track. A timing error signal is supplied when the speed variation exceeds a threshold, thus indicating an unacceptable level of speed variation. A digital synchronizer responds to asynchronous servo data signals from the disk to establish a cell clock signal occurring about a normal frequency, a cell during which only one servo data signal will occur, and a cell data signal which occurs during the cell. The cell clock signal clocks logical operations on a synchronous basis, and servo data signals are reliably captured.