Patents by Inventor Sonarith Chhun

Sonarith Chhun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11682689
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: June 20, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Sonarith Chhun
  • Publication number: 20210111214
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois ROY, Sonarith CHHUN
  • Publication number: 20210111215
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois ROY, Sonarith CHHUN
  • Patent number: 10910428
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 2, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Sonarith Chhun
  • Patent number: 10892291
    Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sonarith Chhun, Gregory Imbert
  • Publication number: 20190189654
    Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sonarith CHHUN, Gregory IMBERT
  • Publication number: 20190181176
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois ROY, Sonarith CHHUN
  • Publication number: 20190088695
    Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 21, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sonarith Chhun, Gregory Imbert
  • Patent number: 9876032
    Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: January 23, 2018
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier, Olivier Weber
  • Publication number: 20170117296
    Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 27, 2017
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier, Olivier Weber
  • Publication number: 20130286540
    Abstract: A method of forming a metal- insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 31, 2013
    Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Patent number: 8424177
    Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 23, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)
    Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Patent number: 8143157
    Abstract: A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: March 27, 2012
    Assignees: NXP B.V., ST Microelectronics (Crolles 2) SAS
    Inventors: Joaquin Torres, Laurent Gosset, Vincent Arnal, Sonarith Chhun
  • Patent number: 7989342
    Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: August 2, 2011
    Inventors: Joaquin Torres, Laurent Gosset, Sonarith Chhun, Vincent Arnal
  • Publication number: 20110080686
    Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
    Type: Application
    Filed: May 6, 2010
    Publication date: April 7, 2011
    Applicants: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)
    Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Publication number: 20100120243
    Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element.
    Type: Application
    Filed: March 3, 2008
    Publication date: May 13, 2010
    Inventors: Joaquin Torres, Laurent Gosset, Sonarith Chhun, Vincent Arnal
  • Publication number: 20100059889
    Abstract: The present invention relates to a method for fabricating a semiconductor device. For improving the adhesion between a copper-containing interconnect element and a diffusion barrier on top of it, a first dielectric layer (108) of a first dielectric material is deposited on an exposed surface (102.1) of the interconnect element. Susequently, particles (110) are implanted into the first dielectric layer and the interconnect element (102) so as to let the interconnect material mix with the first dielectric material in a first interface region (102.2) between the interconnect element and the first dielectric layer.
    Type: Application
    Filed: December 7, 2007
    Publication date: March 11, 2010
    Applicant: NXP, B.V.
    Inventors: Laurent Georges Gosset, Joaquin Torres, Sonarith Chhun
  • Publication number: 20100044865
    Abstract: A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.
    Type: Application
    Filed: November 27, 2007
    Publication date: February 25, 2010
    Applicant: NXP B.V.
    Inventors: Joaquin Torres, Laurent Gosset, Vincent Arnal, Sonarith Chhun
  • Patent number: 7630191
    Abstract: A capacitor formed in an insulating porous material.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: December 8, 2009
    Assignee: STMicroelectronics Crolles 2 SAS
    Inventors: Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Publication number: 20090197405
    Abstract: There is described a method of forming a barrier layer (6, 110) over a surface of a copper line (3, 107) embedded in a dielectric material (2, 100) in an interconnect structure for a semiconductor device. The barrier layer (6, 110) is selectively deposited over the surface of the copper line (3, 107) by a vapour deposition step and the surface of the dielectric material (2, 100) is treated prior to the vapour deposition step to inhibit deposition of the barrier layer (6, 110) there on during the vapour deposition step. Preferably, the vapour deposition step comprises atomic layer deposition.
    Type: Application
    Filed: December 4, 2006
    Publication date: August 6, 2009
    Applicant: NXP B.V.
    Inventors: Wim Besling, Sonarith Chhun