Patents by Inventor Sonarith Chhun
Sonarith Chhun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11682689Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: GrantFiled: December 21, 2020Date of Patent: June 20, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Sonarith Chhun
-
Publication number: 20210111214Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois ROY, Sonarith CHHUN
-
Publication number: 20210111215Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois ROY, Sonarith CHHUN
-
Patent number: 10910428Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: GrantFiled: December 7, 2018Date of Patent: February 2, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Sonarith Chhun
-
Patent number: 10892291Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.Type: GrantFiled: February 26, 2019Date of Patent: January 12, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Sonarith Chhun, Gregory Imbert
-
Publication number: 20190189654Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.Type: ApplicationFiled: February 26, 2019Publication date: June 20, 2019Applicant: STMicroelectronics (Crolles 2) SASInventors: Sonarith CHHUN, Gregory IMBERT
-
Publication number: 20190181176Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: ApplicationFiled: December 7, 2018Publication date: June 13, 2019Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois ROY, Sonarith CHHUN
-
Publication number: 20190088695Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.Type: ApplicationFiled: September 18, 2017Publication date: March 21, 2019Applicant: STMicroelectronics (Crolles 2) SASInventors: Sonarith Chhun, Gregory Imbert
-
Patent number: 9876032Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.Type: GrantFiled: October 18, 2016Date of Patent: January 23, 2018Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier, Olivier Weber
-
Publication number: 20170117296Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.Type: ApplicationFiled: October 18, 2016Publication date: April 27, 2017Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier, Olivier Weber
-
Publication number: 20130286540Abstract: A method of forming a metal- insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.Type: ApplicationFiled: March 14, 2013Publication date: October 31, 2013Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
-
Patent number: 8424177Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.Type: GrantFiled: May 6, 2010Date of Patent: April 23, 2013Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
-
Patent number: 8143157Abstract: A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.Type: GrantFiled: November 27, 2007Date of Patent: March 27, 2012Assignees: NXP B.V., ST Microelectronics (Crolles 2) SASInventors: Joaquin Torres, Laurent Gosset, Vincent Arnal, Sonarith Chhun
-
Patent number: 7989342Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element.Type: GrantFiled: March 3, 2008Date of Patent: August 2, 2011Inventors: Joaquin Torres, Laurent Gosset, Sonarith Chhun, Vincent Arnal
-
Publication number: 20110080686Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.Type: ApplicationFiled: May 6, 2010Publication date: April 7, 2011Applicants: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
-
Publication number: 20100120243Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element.Type: ApplicationFiled: March 3, 2008Publication date: May 13, 2010Inventors: Joaquin Torres, Laurent Gosset, Sonarith Chhun, Vincent Arnal
-
Publication number: 20100059889Abstract: The present invention relates to a method for fabricating a semiconductor device. For improving the adhesion between a copper-containing interconnect element and a diffusion barrier on top of it, a first dielectric layer (108) of a first dielectric material is deposited on an exposed surface (102.1) of the interconnect element. Susequently, particles (110) are implanted into the first dielectric layer and the interconnect element (102) so as to let the interconnect material mix with the first dielectric material in a first interface region (102.2) between the interconnect element and the first dielectric layer.Type: ApplicationFiled: December 7, 2007Publication date: March 11, 2010Applicant: NXP, B.V.Inventors: Laurent Georges Gosset, Joaquin Torres, Sonarith Chhun
-
Publication number: 20100044865Abstract: A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.Type: ApplicationFiled: November 27, 2007Publication date: February 25, 2010Applicant: NXP B.V.Inventors: Joaquin Torres, Laurent Gosset, Vincent Arnal, Sonarith Chhun
-
Patent number: 7630191Abstract: A capacitor formed in an insulating porous material.Type: GrantFiled: February 13, 2007Date of Patent: December 8, 2009Assignee: STMicroelectronics Crolles 2 SASInventors: Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
-
Publication number: 20090197405Abstract: There is described a method of forming a barrier layer (6, 110) over a surface of a copper line (3, 107) embedded in a dielectric material (2, 100) in an interconnect structure for a semiconductor device. The barrier layer (6, 110) is selectively deposited over the surface of the copper line (3, 107) by a vapour deposition step and the surface of the dielectric material (2, 100) is treated prior to the vapour deposition step to inhibit deposition of the barrier layer (6, 110) there on during the vapour deposition step. Preferably, the vapour deposition step comprises atomic layer deposition.Type: ApplicationFiled: December 4, 2006Publication date: August 6, 2009Applicant: NXP B.V.Inventors: Wim Besling, Sonarith Chhun