Abstract: The present invention relates to a malicious code blocking method using a management system for monitoring a state of a vaccine, and more specifically, to a malicious code blocking method using a management system for monitoring a state of a vaccine, in which the management system connected through the Internet monitors in real-time whether or not a vaccine program installed in an individual user terminal normally operates and transmits an alarm to a user when the vaccine program does not operate normally, thereby removing a malicious code. According to the present invention, because an error or a paralyzed state of a vaccine program which cannot be easily understood by general users is informed in real-time, the vaccine program can be promptly normalized regardless of the knowledge and interest of a user, and thus it is effective in that infection and additional damage of the malicious code can be prevented.

Abstract: A scheduling apparatus for dynamically setting a size of a rotating register of a local register file during runtime ids provided. The scheduling apparatus may include a determiner configured to determine whether a non-rotating register of a central register file is sufficient to schedule a program loop; a selector configured to select at least one local register file to which a needed non-rotating register is allocated in response to a determination that the non-rotating register of a central register file has a size which is sufficient to loop a program loop; a scheduler configured to schedule a non-rotating register of the at least one selected local register file.

Abstract: An apparatus and method for calculating a physical address of a register in a processor are provided. The apparatus includes an offset calculator configured to calculate an offset between the physical address and a logical address of the register, based on a current iteration number and a size of a rotating register; an address calculator configured to calculate the physical address of the register by adding the calculated offset to the logical address of the register; and an address corrector configured to output a final physical address of the register based on the calculated physical address and the size of the rotating register.

Abstract: A debugging apparatus and method are provided. The debugging apparatus may include a breakpoint setting unit configured to store a first instruction corresponding to a breakpoint in a table, stop a program currently being executed, and insert a breakpoint instruction including current location information of the first instruction into the breakpoint; and an instruction execution unit configured to selectively execute one of the breakpoint instruction and the first instruction according to a value of a status bit.

Abstract: An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.

Abstract: A memory managing apparatus and method are provided. The memory managing apparatus may determine, based on a pointer indicator bit, the target memory area on which garbage collection is to be performed, and may perform the garbage collection on the target memory area. The memory managing apparatus may generate the pointer indicator bit and store the generated pointer indicator bit in a pointer field.

Abstract: A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation.

Abstract: Provided is a technique for improving the transfer latency of vector register file data when an interrupt is generated. According to an aspect, when interrupt occurs, a core determines whether to store vector register file data currently being executed in a first memory or in a second memory based on whether or not the first memory can store the vector register file data therein. In response to not being able to store the vector register file data in the first memory, a data transfer unit, which is implemented as hardware, is provided to store vector register file data in the second memory.

Abstract: A transcoding device receives an input stream representing media information designated for display at a sink device. The transcoding device generates multiple display streams based on the input stream, wherein each of the display streams has a different transmission characteristic, such as a different bit rate or resolution. The transcoding device selects one of the generated display streams based on a network characteristic, such as a bandwidth or latency, and communicates the selected stream to the network for transmission to the sink device. In response to a change in the network characteristic, a different one of the generated display streams is selected and communicated to the network for transmission to the sink device.

Abstract: The present invention provides methods and materials for isolating, purifying, and/or enriching the concentration of compounds having one or more phosphate groups and/or derivatives thereof, including but not limited to phosphorylated peptides and/or phosphorylated proteins. In some aspects, the present invention provides nanostructured enrichment materials, such as metal oxide mesoporous materials, that selectively and reversibly bind with phosphorylated compounds with high specificity and are capable of controlled release of phosphorylated compounds bound to their active surfaces. Mesoporous materials of the present invention also provide enrichment materials having large active surface areas that provide for higher loading capacities for phosphorylated peptides and proteins relative to conventional affinity based methods.

Abstract: A technique for minimizing overhead caused by copying or moving a value from one cluster to another cluster is provided. A number of operations, for example, a mov operation for moving or copying a value from one cluster to another cluster and a normal operation may be executed concurrently. Accordingly, access to a register file outside of the cluster may be reduced and the performance of code may be improved.

Abstract: The use of coal fields as subsurface bioreactors for producing sustainable methane gas from terrestrial sources of biomass is described. Microbial presence is determined for a target coal formation, and tracers are injected to determine permeability, porosity, volume, and minimum and a maximum material injection rates. At least one injection well and at least one circulation well effective for generating an injection rate between the minimum and maximum injection rates are provided for injecting a solution of biodegradable materials into the coal seam. A chosen quantity of biodegradable materials is allowed to be digested, fermented and converted by microbial action within the coal seam. Methane gas is extracted through producing and injecting wells, although pumping will enhance gas recovery.

Abstract: An apparatus and method are provided to minimize an overhead caused by mode conversion by processing parts that cannot be subject to software pipelining. A processor is configured to execute code including a first part that is able to be subject to software pipelining in the code, and a second part that is disable to be subject to software pipelining in the code, the second part including a data part and a control part. The processor is further configured to execute the first part, and the data part of the second part in a first execution mode, and to execute the control part of the second part in a second execution mode. When the first part and the data part, the data part and the first part, or different data parts are successively executed, the processor processes the code in the first execution mode without entering the second execution mode.

Abstract: Provided is a technique that is capable of efficiently compressing instructions by inserting instruction compression bits into valid instruction bundles and deleting no operation (NOP) instruction bundles. Accordingly, the number of instructions that can be parallel-processed in a processor may be increased.

Abstract: The present invention provides metal silicide nanowires, including metallic, semiconducting, and ferromagnetic semiconducting transition metal silicide nanowires. The nanowires are grown using either chemical vapor deposition (CVD) or chemical vapor transport (CVT) on silicon substrates covered with a thin silicon oxide film, the oxide film desirably having a thickness of no greater than about 5 nm and, desirably, no more than about 2 nm (e.g., about 1-2 nm). The metal silicide nanowires and heterostructures made from the nanowires are well-suited for use in CMOS compatible wire-like electronic, photonic, and spintronic devices.

Abstract: Methods of stimulating microbial consortia, such as microbial consortia in a geological formation, such as comprising methanogens and other bacteria, for producing methane and other fuels or fuel precursors from coal or other carbonaceous materials, are disclosed along with methods for increasing bioconversion of carbonaceous materials, such as coal, into methane and other useful hydrocarbon products, wherein the consortia respond to electrical stimulation, either physical or chemical.

Abstract: An apparatus and method for encoding/decoding an input video complied with a fixed frame rate standard and adjusting bit-stream of an encoded/decoded video in real-time. The apparatus comprises a video encoder, a control circuit, an interface, and a buffer. The control circuit is used for monitoring the utility status of the buffer and thereby controlling the operation of the video encoder to achieve real-time adjustable time-varying throughput for various transmission environments.

Abstract: Provided is an apparatus and method capable of processing code to which a software pipelining is not applicable, in a CGA mode. The apparatus may include a processing unit that has a very long instruction word (VLIW) mode and a coarse-grained array (CGA) mode, and an adjusting unit configured to detect a target region to which software pipelining is not applicable, in code to be executed by the processing unit. The adjusting unit may selectively map the detected target region to one of the VLIW mode and the CGA mode according to a schedule length of the detected target region.

Abstract: A method of processing an interleaved video including a plurality of fields includes receiving a top field and a bottom field successively; selecting one of the top field and the bottom field as a selected field; and generating an interpolated field for replacing an unselected field of the top field and the bottom field, wherein a field motion between the selected field and the interpolated field is less than a field motion between the top field and the bottom field.