Abstract: A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.

Abstract: A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

Abstract: A method for manufacturing a distributed feedback laser array includes: forming a bottom separate confinement layer on a substrate; forming a quantum-well layer on the bottom separate confinement layer; forming a selective-area epitaxial dielectric mask pattern on the quantum-well layer; forming a top separate confinement layer on the quantum-well layer through selective-area epitaxial growth using the selective-area epitaxial dielectric mask pattern, the top separate confinement layer having different thicknesses for different laser units; removing the selective-area epitaxial dielectric mask pattern; forming an optical grating on the top separate confinement layer; and growing a contact layer on the optical grating. The present disclosure achieves different emission wavelengths for different laser units without significantly affect emission performance of the quantum-well material.

Abstract: A photonic-crystal surface-emitting laser (PCSEL) includes a gain medium electromagnetically coupled to a photonic crystal whose energy band structure exhibits a Dirac cone of linear dispersion at the center of the photonic crystal's Brillouin zone. This Dirac cone's vertex is called a Dirac point; because it is at the Brillouin zone center, it is called an accidental Dirac point. Tuning the photonic crystal's band structure (e.g., by changing the photonic crystal's dimensions or refractive index) to exhibit an accidental Dirac point increases the photonic crystal's mode spacing by orders of magnitudes and reduces or eliminates the photonic crystal's distributed in-plane feedback. Thus, the photonic crystal can act as a resonator that supports single-mode output from the PCSEL over a larger area than is possible with conventional PCSELs, which have quadratic band edge dispersion. Because output power generally scales with output area, this increase in output area results in higher possible output powers.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

Abstract: A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.

Abstract: Methods, systems and apparatuses for selecting which of a plurality of sensors to use for location detection of a mobile device are disclosed. One method includes activating lowest-power location-related sensors of the mobile device at power up of a mobile device, and activating medium-power location-related sensors of the mobile device upon detection of motion of the mobile device and/or a change in a wireless connection to the mobile device.

Abstract: A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.

Abstract: A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.

Abstract: Methods, systems and apparatuses for using wireless access points to identify points of interest (POIs), are disclosed. One embodiment includes a method of using wireless access points to identify points of interest (POIs). The method includes collecting wireless access data points, wherein the wireless access data points comprise at least one wireless access point signature of at least one wireless access element of the wireless access points, analyzing the wireless access data points over a time window, comprising identifying segments within the time window, and matching a point of interest (POI) with each identified segment.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

Abstract: Methods, systems and apparatus for ranking potential points of interest (POIs) of a user stay are disclosed. One system includes an upstream server connected through a network to a mobile device. At least one of the upstream server and a controller of the mobile device is operative to estimate a location of a user stay of the mobile device, access a database of POIs, and parameters of the POIs, and generate a ranking score for a plurality of POIs based on a weighted comparison of each of the parameters of the POIs with corresponding parameters of the user stay.

Abstract: Methods, systems and apparatuses for automatically determining user stays of a user of a mobile device are disclosed. One embodiment includes a network server operative to receive sensed location information of a mobile device. Further, the network server and/or a controller of the mobile device are operative to determine the mobile device is within a specific distance of a specific location for at least specific minimum time duration based on the location information, determine a start time of a user stay based on the location information, the specific location and the specific distance, and determine an end time of the user stay based on the location information, the specific location and the specific distance.

Abstract: Methods, systems and apparatuses for real-time determination of user stays of a mobile device are disclosed. One computer-implemented method includes receiving, by a server, an incoming stream of location point information of the mobile device. Further, the method includes continuously calculating, by the server, a current centroid of a current user stay based on a location point of a start time of the current user stay, each location point occurring between the start time and a current incoming location point, until an outlier location point is detected, wherein the outlier is detected if located more than a threshold distance away from the current centroid.

Abstract: A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.

Abstract: Methods, systems and apparatuses for authenticating a user of a mobile device are disclosed. One method includes tracking a plurality of locations of the mobile device, tracking motion behavior of the mobile device, and generating a user profile for the user over a period of time based on the tracked plurality of locations and the tracked motion behavior. A present user of the mobile device is authenticated based on a comparison of the user profile with a present user profile of the present user, wherein the present user profile comprises recent location information of the mobile device and recent motion behavior of the mobile device.

Abstract: A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.