Patents by Inventor Song Liang

Song Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hybrid Process for Forming Metal Gates of MOS Devices
    Publication number: 20090230479
    Abstract: A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.
    Type: Application
    Filed: March 12, 2008
    Publication date: September 17, 2009
    Inventors: Peng-Fu Hsu, Yong-Tian Hou, Ssu-Yi Li, Kuo-Tai Huang, Mong Song Liang
  • MOS Devices with Partial Stressor Channel
    Publication number: 20090224337
    Abstract: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.
    Type: Application
    Filed: May 18, 2009
    Publication date: September 10, 2009
    Inventors: Ming-Hua Yu, Mong-Song Liang, Tze-Liang Lee, Jr-Hung Li
  • Determining throughput between hosts
    Patent number: 7564781
    Abstract: An apparatus and method of determining throughput between a first host and a second host of at least one network is disclosed. The method includes the first host intentionally corrupting ICMP packets by manipulating a checksum of the ICMP packets. The first host sends the corrupted ICMP packets to the second host through the at least one network. The first host additionally sends non-corrupted ICMP packets to the second host. Based on responses from second host to the ICMP packets, the first host estimates a throughput between the first host and the second host. The throughput includes a first direction throughput from the first host to the second host, a second direction throughput from the second host to the first host, and a round trip throughput between the first host and the second host.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: July 21, 2009
    Assignee: Tropos Networks, Inc.
    Inventor: Sam Song Liang
  • MOS devices with partial stressor channel
    Patent number: 7554110
    Abstract: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: June 30, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Mong-Song Liang, Tze-Liang Lee, Jr-Hung Li
  • Super anneal for process induced strain modulation
    Patent number: 7528028
    Abstract: A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: May 5, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mong Song Liang, Chien-Hao Chen, Chun-Feng Nieh, Pang-Yen Tsai, Tze-Liang Lee, Shih-Chang Chen
  • Method for fabricating dual-gate semiconductor device
    Patent number: 7510940
    Abstract: A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: March 31, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Nan Yeh, Mong Song Liang, Ryan Chia-Jen Chen, Yuan-Hung Chiu
  • Method for forming composite barrier layer
    Publication number: 20090047780
    Abstract: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.
    Type: Application
    Filed: October 10, 2008
    Publication date: February 19, 2009
    Inventors: Cheng-Lin Huang, Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Chao-Hsien Peng, Li-Lin Su, Jing-Cheng Lin, Shao-Lin Shue, Mong-Song Liang
  • Semiconductor Device with both I/O and Core Components and Method of Fabricating Same
    Publication number: 20080315320
    Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Inventors: Chung Long Cheng, Sheng-Chen Chung, Kong-Beng Thei, Harry Chuang, Mong Song Liang
  • Strained Isolation Regions
    Publication number: 20080303102
    Abstract: An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Inventors: Mong-Song Liang, Tze-Liang Lee, Kuo-Tai Huang, Chao-Cheng Chen, Hao-Ming Lien, Chih-Tang Peng
  • Layout methods of integrated circuits having unit MOS devices
    Publication number: 20080296691
    Abstract: A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 4, 2008
    Inventors: Harry Chuang, Kong-Beng Thei, Jen-Bin Hsu, Chung Long Cheng, Mong Song Liang
  • Composite barrier layer
    Patent number: 7453149
    Abstract: A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: November 18, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Lin Huang, Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Chao-Hsien Peng, Li-Lin Su, Jing-Cheng Lin, Shao-Lin Shue, Mong-Song Liang
  • Adhesion of copper and etch stop layer for copper alloy
    Patent number: 7443029
    Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: October 28, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing Cheng Lin, Ching-Hua Hsieh, Shau-Lin Shue, Mong-Song Liang
  • Contact Scheme for MOSFETs
    Publication number: 20080258228
    Abstract: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.
    Type: Application
    Filed: August 2, 2007
    Publication date: October 23, 2008
    Inventors: Harry Chuang, Kong-Beng Thei, Mong Song Liang, Jung-Hui Kao, Sheng-Chen Chung, Chung Long Cheng, Shun-Jang Liao
  • 3-Dimensional Device Design Layout
    Publication number: 20080263492
    Abstract: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.
    Type: Application
    Filed: August 2, 2007
    Publication date: October 23, 2008
    Inventors: Harry Chuang, Kong-Beng Thei, Mong Song Liang, Sheng-Chen Chung, Chih-Tsung Yao, Jung-Hui Kao, Chung Long Cheng, Gary Shen, Gwan Sin Chang
  • METHODS FOR FORMING TRANSISTORS WITH HIGH-K DIELECTRIC LAYERS AND TRANSISTORS FORMED THEREFROM
    Publication number: 20080254588
    Abstract: A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such that the at least partially nitridized gate dielectric layer has a nitrogen concentration between about 0.5 atomic percentage (at. %) and about 20 at %.
    Type: Application
    Filed: April 16, 2007
    Publication date: October 16, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry Chuang, Kong-Beng Thei, Hung-Chih Tsai, M. Y. Wu, Mong-Song Liang
  • Method for fabricating semiconductor device
    Publication number: 20080242108
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 2, 2008
    Inventors: Weng Chang, Fong-Yu Yen, Hun-Jan Tao, Mong-Song Liang
  • Method for fabricating dual-gate semiconductor device
    Publication number: 20080197420
    Abstract: A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.
    Type: Application
    Filed: February 16, 2007
    Publication date: August 21, 2008
    Inventors: Chen-Nan Yeh, Mong Song Liang, Ryan Chia-Jen Chen, Yuan-Hung Chiu
  • Method of making FUSI gate and resulting structure
    Patent number: 7410854
    Abstract: Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stack height, removing the second polysilicon layer and the etch stop layer, and reacting the first polysilicon layer with a metal to fully silicide the first polysilicon layer. Fully silicided (FUSI) gates can hence be formed with uniform gate height. The thin first polysilicon layer allows for siliciding with a lower thermal budge and with better uniformity of the silicide concentration throughout the layer.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: August 12, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Gi Yao, Hun-Jan Tao, Shih-Chang Chen, Mong-Song Liang
  • Backside contacts for MOS devices
    Patent number: 7402866
    Abstract: A semiconductor structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate dielectric over the first surface of the semiconductor substrate, a gate electrode over the gate dielectric, a source/drain region having at least a portion in the semiconductor substrate, a dielectric layer having a first surface and a second surface opposite the first surface wherein the first surface of the dielectric layer adjoins the second surface of the semiconductor substrate, and a contact plug in the dielectric layer, wherein the contact plug extends from a bottom side of the source/drain region to the second surface of the dielectric layer.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: July 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mong Song Liang, Hun-Jan Tao
  • Portable reading lamp
    Patent number: D582590
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: December 9, 2008
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Wei Ding, Song Liang, Wen Gu, Guanjun Yang, Bo Liu, Xuan Zhu, Vincent Mathieu Vaucelle, Sean Patrick Hughes, Hendrikus Albertus Adrianus Maria de Ruijter, Cornelis Reinder Ronda