Abstract: A gate drive circuit that drives a power device by controlling charge and discharge of gate capacitance of the power device includes: a first semiconductor switch that charges the gate capacitance by being brought into conduction according to a first control signal; a second semiconductor switch that discharges the gate capacitance by being brought into conduction according to a second control signal; and a slew rate control circuit that is connected between a gate of the power device and a ground line, and controls a slew rate during discharge. The slew rate control circuit includes a capacitor and a third semiconductor switch connected in series. The third semiconductor switch is brought into conduction according to the second control signal.

Abstract: An electromagnetic resonance coupler includes a first transmission line on a top surface of a first dielectric layer, and a second transmission line on a top surface of a second dielectric layer. The first transmission line includes first and second resonance lines and first and second input-output lines. The second transmission line includes third and fourth resonance lines and third and fourth input-output lines. Third and fourth ground parts are provided separated from each other on the top surface of the second dielectric layer or the top surface of the first dielectric layer. The first resonance line and the third ground part are connected via a third connector, and the fourth resonance line and the fourth ground part are connected via a fourth connector.

Abstract: A gate driving circuit that controls a switching element includes: a startup switch which is provided between a gate voltage source and an output terminal; a termination switch which is provided between the output terminal and an output ground terminal; a startup resistor provided between a gate and a source of the startup switch; and a termination resistor provided between a gate and a source of the termination switch. At least one of the startup resistor or the termination resistor is configured to adjust a resistance value.

Abstract: A signal transmission apparatus includes: a first lead frame; a second lead frame spaced from the first lead frame; a primary semiconductor chip electrically connected to the first lead frame; a secondary semiconductor chip electrically connected to the second lead frame; and a signal isolator through which a signal is isolatedly transmitted from the primary semiconductor chip to the secondary semiconductor chip, the signal isolator having a first main surface that is bonded to both the first lead frame and the second lead frame.

Abstract: A signal transmission device comprises: a first lead frame having a first major surface and a second major surface opposite to the first major surface; a second lead frame having a third major surface and a fourth major surface and isolated from the first lead frame, the fourth major surface located opposite to the third major surface; a transmission circuit that sends a transmission signal, the transmission circuit located on the first major surface of the first lead frame; a receiving circuit located on the third major surface of the second lead frame; and an electromagnetic resonance coupler located across between the second major surface of the first lead frame and the fourth major surface of the second lead frame to transmit the transmission signal, sent by the transmission circuit, to the receiving circuit in a contactless manner.

Abstract: A signal transmission apparatus includes: a first lead frame; a second lead frame spaced from the first lead frame; a primary semiconductor chip electrically connected to the first lead frame; a secondary semiconductor chip electrically connected to the second lead frame; and a signal isolator through which a signal is isolatedly transmitted from the primary semiconductor chip to the secondary semiconductor chip, the signal isolator having a first main surface that is bonded to both the first lead frame and the second lead frame.

Abstract: A signal transmission device comprises: a first lead frame having a first major surface and a second major surface opposite to the first major surface; a second lead frame having a third major surface and a fourth major surface and isolated from the first lead frame, the fourth major surface located opposite to the third major surface; a transmission circuit that sends a transmission signal, the transmission circuit located on the first major surface of the first lead frame; a receiving circuit located on the third major surface of the second lead frame; and an electromagnetic resonance coupler located across between the second major surface of the first lead frame and the fourth major surface of the second lead frame to transmit the transmission signal, sent by the transmission circuit, to the receiving circuit in a contactless manner.

Abstract: A nitride semiconductor structure includes a nitride semiconductor layer having a principal plane and including a nitride semiconductor. The normal to the principal plane of the nitride semiconductor layer is inclined at 5 degrees or more and 17 degrees or less with respect to the [11-22] axis of the nitride semiconductor constituting the nitride semiconductor layer in the direction of the +c-axis of the nitride semiconductor. The nitride semiconductor structure may further include a substrate having a principal plane which supports the nitride semiconductor layer on the principal plane. The substrate may include any one selected from the group consisting of a nitride semiconductor, sapphire, and Si.

Abstract: A nitride semiconductor device according to one embodiment of the present disclosure includes: a substrate; a first nitride semiconductor layer supported by the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a source-side nitride semiconductor regrowth layer which is located on a source-side recess region; a drain-side nitride semiconductor regrowth layer which is located on a drain-side recess region located apart from the source-side recess region; a first diffusion layer which is disposed in the first nitride semiconductor layer and contains Ge diffused from the source-side nitride semiconductor regrowth layer; and a second diffusion layer which is disposed in the first nitride semiconductor layer and contains Ge diffused from the drain-side nitride semiconductor regrowth layer.

Abstract: A diamond multilayer structure comprises: a nitride semiconductor layer that have a first main surface and a second main surface and comprises a nitride semiconductor having a wurtzite structure and containing B; and a diamond layer located on the first main surface of the nitride semiconductor layer.

Abstract: A nitride semiconductor device according to one embodiment of the present disclosure includes: a substrate; a first nitride semiconductor layer supported by the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a source-side nitride semiconductor regrowth layer which is located on a source-side recess region; a drain-side nitride semiconductor regrowth layer which is located on a drain-side recess region located apart from the source-side recess region; a first diffusion layer which is disposed in the first nitride semiconductor layer and contains Ge diffused from the source-side nitride semiconductor regrowth layer; and a second diffusion layer which is disposed in the first nitride semiconductor layer and contains Ge diffused from the drain-side nitride semiconductor regrowth layer.

Abstract: A nitride semiconductor structure includes: a plurality of crystal growth seed regions formed of a nitride semiconductor, of which the principal surface is an m-plane and which extends to a range that defines an angle of not less than 0 degrees and not more than 10 degrees with respect to an a-axis; and a laterally grown region formed of a nitride semiconductor which has extended in a c-axis direction from each of the plurality of crystal growth seed regions. An S width that is the spacing between adjacent ones of the plurality of crystal growth seed regions is at least 20 ?m.

Abstract: A nitride semiconductor structure includes a nitride semiconductor layer having a principal plane and including a nitride semiconductor. The normal to the principal plane of the nitride semiconductor layer is inclined at 5 degrees or more and 17 degrees or less with respect to the [11-22] axis of the nitride semiconductor constituting the nitride semiconductor layer in the direction of the +c-axis of the nitride semiconductor. The nitride semiconductor structure may further include a substrate having a principal plane which supports the nitride semiconductor layer on the principal plane. The substrate may include any one selected from the group consisting of a nitride semiconductor, sapphire, and Si.

Abstract: A nitride-based semiconductor light-emitting device includes: a nitride-based semiconductor multilayer structure including a p-type semiconductor region having an m-plane as a growing plane; and an Ag electrode provided so as to be in contact with the growing plane of the p-type semiconductor region, wherein the Ag electrode has a thickness in a range of not less than 200 nm and not more than 1,000 nm; an integral intensity ratio of an X-ray intensity of a (111) plane on the growing plane of the Ag electrode to that of a (200) plane is in a range of not less than 20 and not more than 100; and the Ag electrode has a reflectance of not less than 70%.

Abstract: A nitride semiconductor multilayer structure includes a sapphire substrate having an m-plane principal surface with an off-angle ?, and a mask layer including first and second side surface portions that sandwich each exposed region. In a cross section parallel to the m- and c-axes, points at which the first and second side surface portions meet the principal surface are respectively points A and B, a point at which the first side surface portion intersects a line passing through point B and forming an angle of 58°?? with the principal surface is C, a distance between a line passing through point C and perpendicular to the principal surface and a line passing through point B and perpendicular to the principal surface is W, and a height of the first side surface portion is H. Then H?W·tan(58°??)).

Abstract: A structure for growth of a nitride semiconductor layer which is disclosed in this application includes: a sapphire substrate of which growing plane is an m-plane; and a plurality of ridge-shaped nitride semiconductor layers provided on the growing plane of the sapphire substrate, wherein a bottom surface of a recessed portion provided between respective ones of the plurality of ridge-shaped nitride semiconductor layers is the m-plane of the sapphire substrate, the growing plane of the plurality of ridge-shaped nitride semiconductor layers is an m-plane, and an absolute value of an angle between an extending direction of the plurality of ridge-shaped nitride semiconductor layers and a c-axis of the sapphire substrate is not less than 0° and not more than 35°.

Abstract: A nitride semiconductor structure includes: a plurality of crystal growth seed regions formed of a nitride semiconductor, of which the principal surface is an m-plane and which extends to a range that defines an angle of not less than 0 degrees and not more than 10 degrees with respect to an a-axis; and a laterally grown region formed of a nitride semiconductor which has extended in a c-axis direction from each of the plurality of crystal growth seed regions. An S width that is the spacing between adjacent ones of the plurality of crystal growth seed regions is at least 20 ?m.

Abstract: A structure for growth of a nitride semiconductor layer which is disclosed in this application includes: a sapphire substrate of which growing plane is an m-plane; and a plurality of ridge-shaped nitride semiconductor layers provided on the growing plane of the sapphire substrate, wherein a bottom surface of a recessed portion provided between respective ones of the plurality of ridge-shaped nitride semiconductor layers is the m-plane of the sapphire substrate, the growing plane of the plurality of ridge-shaped nitride semiconductor layers is an m-plane, and an absolute value of an angle between an extending direction of the plurality of ridge-shaped nitride semiconductor layers and a c-axis of the sapphire substrate is not less than 0° and not more than 35°.

Abstract: A structure for growth of a nitride semiconductor layer which is disclosed in this application includes: a sapphire substrate of which growing plane is an m-plane; and a plurality of ridge-shaped nitride semiconductor layers provided on the growing plane of the sapphire substrate, wherein a bottom surface of a recessed portion provided between respective ones of the plurality of ridge-shaped nitride semiconductor layers is the m-plane of the sapphire substrate, the growing plane of the plurality of ridge-shaped nitride semiconductor layers is an m-plane, and an absolute value of an angle between an extending direction of the plurality of ridge-shaped nitride semiconductor layers and a c-axis of the sapphire substrate is not less than 0° and not more than 35°.

Abstract: A gallium nitride based compound semiconductor light-emitting element according to an embodiment of the present disclosure includes: an n-type gallium nitride based compound semiconductor layer; a p-type gallium nitride based compound semiconductor layer; and an active layer which is arranged between the n- and p-type gallium nitride based compound semiconductor layers. The active layer and the p-type gallium nitride based compound semiconductor layer are m-plane semiconductor layers. The p-type gallium nitride based compound semiconductor layer includes magnesium at a concentration of 2.0×1018 cm?3 to 2.5×1019 cm?3 and oxygen, of which the concentration is 5% to 15% of the concentration of the magnesium.