Abstract: A MOS transistor of the present invention includes a semiconductor substrate of a first conductivity type impurity, a gate insulating layer formed on the semiconductor substrate, gate electrodes formed on the gate insulating layer, and an oxide layer formed by surface oxidation of the gate electrodes. A first spacer is formed on the side wall of the gate electrodes, and a second spacer is formed on the inclined side wall. A first impurity layer of low concentration is formed at a first depth by a second conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate to be self-aligned at the edge of the gate electrode. A second impurity layer of middle concentration is formed at a deeper second depth than the first depth by the second conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate.

Abstract: A manufacturing method of semiconductor devices in which sources and drains define effective channels having lengths which are essentially equal to target length is disclosed. The method includes the steps of forming a gate electrode on a semiconductor substrate, measuring a length of the gate electrode, calculating a lateral diffusion distance using the measured length of the gate electrode and a length of a target effective channel, determining implantation conditions for forming a source and drain having the lateral diffusion distance, and forming the source and drain, by ion implanting in accordance with the implantation conditions. Even though the length of the gate electrode is changed in accordance with a change of the process conditions, sources and drains defining effective channels of a target length can be formed.

Abstract: Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough such that sidewalls of the array of insulating islands are surrounded by the third continuous conductive layer, rows of unaligned spaced apart insulating islands. The array can include rows of unaligned spaced apart insulating islands and columns of unaligned spaced apart insulating islands. The array of unaligned spaced apart insulating islands can also include a first insulating island having a first edge in a first direction and a second insulating island, adjacent to the first insulating island in the first direction having a second edge in the first direction that is unaligned with first edge.

Abstract: In a position controlling apparatus and method for an elevator which controls a position of an elevator in accordance with a velocity command profile consisting of an acceleration region, a uniform velocity region and a deceleration region, a position controlling apparatus and method according to the present invention controls generation of a synchronization position error in the deceleration region.

Abstract: A method for forming a multilevel interconnection between a polycide layer and a polysilicon layer is disclosed. The multilevel interconnection comprises: forming a first impurity-containing conductive layer on a semiconductor substrate; forming a first silicide layer, having a first region thinner than a second region, on the first impurity-containing conductive layer; forming an interlayer dielectric layer in other than the first region; forming a contact hole for exposing the first silicide layer of the first region; and connecting a second impurity-containing conductive layer to the first silicide layer through the contact hole.

Abstract: Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart conductive layers and an array of spaced apart insulating islands in the third continuous conductive layer that extend therethrough such that sidewalls of the insulating islands are surrounded by the third continuous conductive layer. A fourth continuous conductive layer also may be provided between the third continuous conductive layer and the second conductive layer and a second array of spaced apart insulating islands may be provided in the fourth continuous conductive layer, that extend therethrough, such that sidewalls of the insulating islands are surrounded by the fourth continuous conductive layer.

Abstract: A multilevel interconnection between a polycide layer and a polysilicon layer and a method of forming thereof are provided. The multilevel interconnection comprises: a first impurity-containing conductive layer formed on a semiconductor substrate; a first silicide layer, having a first region thinner than a second region, formed on the first impurity-containing conductive layer; an interlayer dielectric layer formed in other than the first region; a contact hole for exposing the first silicide layer of the first region; and a second impurity-containing conductive layer connected to the first silicide layer through the contact hole. Therefore, increases in contact resistance between conductive layers can be prevented.

Abstract: In a bipolar transistor and the manufacturing method thereof, the bipolar transistor includes a first conductive well, an emitter impurity layer formed in the center of the well, a base impurity layer formed in the form of completely surrounding the emitter impurity layer, and a first conductive high-concentration collector impurity layer having an annular shape along the edge of the well, and maintaining a constant interval from the base impurity layer. The first conductive layer formed to be parallel with the high-concentration collector impurity layer is connected therewith through a contact hole, and is connected with the collector electrode through another contact hole. Owing to a simple manufacturing process, the processing time and cost can be reduced. Also, parasitic bipolar transistors are not generated nor is increased collector resistance produced, thereby increasing reliability.

Abstract: A semiconductor memory device is provided for preventing loss of cell data and reduction of a standby current. The semiconductor memory device includes a first conductivity type semiconductor substrate connected to a ground voltage, a first well region of second conductivity type formed over the semiconductor substrate and connected to the ground voltage, a second well region of the first conductivity type embedded in the first well region, a first impurity region of the second conductivity type embedded in the second well region and connected to an input/output pad, and one or more additional impurity regions embedded in the second well region separately from the first impurity region, the one or more additional impurity regions being connected to the ground voltage.

Abstract: An integrated circuit includes a metallic fuse link blown by a laser beam which may enhance the long term reliability of the metallic fuse link. The integrated circuit includes an insulating layer formed on a semiconductor substrate. First and second metal wiring layers each with an end surface and an upper surface are located on the insulating layer. The first and second metal wiring layers are arranged so that the end surface of each metal wiring layer faces the other metal wiring layer. A metallic fuse layer is located on the upper surfaces of the metal wiring layers, on the end surfaces of the metal wiring layers and therebetween to define a metallic fuse link.

Abstract: A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed.

Abstract: A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed.

Abstract: Integrated circuit SRAM cells include a semiconductor substrate having a field region and first, second, third and fourth active regions therein. The first and second active regions each include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The third and fourth active regions each also include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The integrated circuit SRAM cells also include first and second vertically extending gate conductive layers on the semiconductor substrate. The first vertically extending conductive layer extends vertically over the first active region horizontal leg and extends vertically over the third active region horizontal leg. The second vertically extending conductive layer extends vertically over the second active region horizontal leg and extends vertically over the fourth active region horizontal leg.

Abstract: A through-condenser for supplying an accelerating voltage to a magnetron is disclosed, with the magnetron being for generating ultra-high frequency for microwave ovens and broadcasting apparatuses. The condenser includes a grounding plate, a pair of cylindrical ground electrodes, a pair of conductive rods, and a single insulating resin. The grounding plate is provided with a pair of through-holes, and the ground electrodes are inserted into the through-holes of the grounding plate in a conductive manner. The conductive rods respectively consist of a body portion, a tap terminal and an output terminal, and are inserted respectively through the ground electrodes in a non-conductive manner. The resin is injected to serve as an outer casing of the condenser and as a dielectric layer between the ground electrodes and the conductive rods.

Abstract: A self-aligning ion-implantation method for forming multi-gate MOS transistor structures within a semiconductor cell array on a substrate is provided. Each structure includes a plurality of first gate electrode layers and a plurality of second gate electrode layers arranged in an alternating sequence over a channel region between a drain and a source region and insulated from each other.

Abstract: This invention relates to a piercing through type capacitor used in high voltage high frequency wave device, which is comprised of: ceramic disc having two separated electrodes on top surface and common electrode on bottom surface; grounding plate which is made by a locating means of elongated oval shape to be laid with said ceramic disc thereon, an elongated oval protuberance having large elongated oval piercing through opening at central portion, and a number of small piercing through holes around said elongated oval protuberance with keeping a predetermined distance therefrom; insulation case of elongated oval hollow column which is made integrally with upper and lower insulation case for surrounding the ceramic disc at both sides of said grounding plate; a pair of piercing through conductors in which a pair of metal caps which are provided to each of said two separated electrodes on the top surface of said ceramic disc and having protrusions at each periphery are fixed by soldering or welding; a pair of i

Abstract: A nonvolatile semiconductor memory device is provided including a doped semiconductor substrate and three gate conductor layers electrically insulated from each other in the cell area on the substrate. A first floating gate conductor layer is formed on the substrate and covered by a second control gate conductor layer, forming a twofold polycrystalline silicon structure. A third select gate conductor layer is formed along one side wall of the twofold structure of the floating gate and control gate conductor layers, having a side wall spacer structure. The first conductor layer serves as a floating gate; the second conductor layer serves as a control gate; and the third conductor layer serves as a select gate. A field oxide layer is provided to separate cells from each other. The control and the select gates are connected in a region between cells through the field oxide layer. By providing the third conductor in the form of a side wall spacer, the cell area can be greatly reduced.

Abstract: A nonvolatile semiconductor memory device is provided including a doped semiconductor substrate and three gate conductor layers electrically insulated from each other in the cell area on the substrate. A first floating gate conductor layer is formed on the substrate and covered by a second control gate conductor layer, forming a twofold polycrystalline silicon structure. A third select gate conductor layer is formed along one side wall of the twofold structure of the floating gate and control gate conductor layers, having a side wall spacer structure. The first conductor layer serves as a floating gate; the second conductor layer serves as a control gate; and the third conductor layer serves as a select gate. A field oxide layer is provided to separate cells from each other. The control and the select gates are connected in a region between cells through the field oxide layer. By providing the third conductor in the form of a side wall spacer, the cell area can be greatly reduced.

Abstract: Integrated circuit SRAM cells include a semiconductor substrate having a field region and first, second, third and fourth active regions therein. The first and second active regions each include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The third and fourth active regions each also include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The integrated circuit SRAM cells also include first and second vertically extending gate conductive layers on the semiconductor substrate. The first vertically extending conductive layer extends vertically over the first active region horizontal leg and extends vertically over the third active region horizontal leg. The second vertically extending conductive layer extends vertically over the second active region horizontal leg and extends vertically over the fourth active region horizontal leg.