Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

Abstract: A method is provided for forming a semiconductor device. The method includes forming a vertical film stack containing a sacrificial layer on a substrate and dielectric layers alternatingly and repeatedly stacked on the sacrificial layer, removing the sacrificial layer to form a horizontal channel above the substrate, depositing a conformal dielectric layer in the horizontal channel, etching trenches in the vertical film stack that connect to the horizontal channel. The method further includes removing the conformal dielectric layer from the horizontal channel, filling the horizontal channel and the trenches with a first electrically conductive material, removing the first electrically conductive material from the trenches, and filling the trenches with a second electrically conductive material.

Abstract: Methods are disclosed that selectively deposit a protective material on the top regions of patterned photoresist layers, such patterned EUV photoresist layers, to provide a protective cap that reduces erosion damage during etch processes used for pattern transfer. Some deposition of the protective material on the sidewalls of the patterned photoresist layer is acceptable, and any deposition of the protective material on the underlying layer below the patterned photoresist layer is preferably thinner than the deposition at the top of the photoresist pattern. Further, the selective deposition of protective caps can be implemented, for example, through the application of high-rotation speeds to spatial atomic layer deposition (ALD) techniques. The selective deposition of protective caps increases the flexibility of options to improve etch resistance for various processes/materials.

Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.

Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

Abstract: Methods are disclosed that selectively deposit a protective material on the top regions of patterned photoresist layers, such patterned EUV photoresist layers, to provide a protective cap that reduces erosion damage during etch processes used for pattern transfer. Some deposition of the protective material on the sidewalls of the patterned photoresist layer is acceptable, and any deposition of the protective material on the underlying layer below the patterned photoresist layer is preferably thinner than the deposition at the top of the photoresist pattern. Further, the selective deposition of protective caps can be implemented, for example, through the application of high-rotation speeds to spatial atomic layer deposition (ALD) techniques. The selective deposition of protective caps increases the flexibility of options to improve etch resistance for various processes/materials.

Abstract: A substrate processing method for forming a self-aligned contact using selective SiO2 deposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiO2 layer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.

Abstract: A method is provided for forming a semiconductor device. The method includes forming a vertical film stack containing a sacrificial layer on a substrate and dielectric layers alternatingly and repeatedly stacked on the sacrificial layer, removing the sacrificial layer to form a horizontal channel above the substrate, depositing a conformal dielectric layer in the horizontal channel, etching trenches in the vertical film stack that connect to the horizontal channel. The method further includes removing the conformal dielectric layer from the horizontal channel, filling the horizontal channel and the trenches with a first electrically conductive material, removing the first electrically conductive material from the trenches, and filling the trenches with a second electrically conductive material.

Abstract: Methods are described for protecting cobalt (Co) metal plugs used for making electrical connections within a semiconductor device. In one example, method includes providing a substrate containing a Co metal plug in a dielectric layer, and selectively forming a ruthenium (Ru) metal cap layer on the Co metal plug. In another example, the method includes providing a substrate containing a Co metal plug in a first dielectric layer, selectively forming a Ru metal cap layer on the Co metal plug, depositing a second dielectric layer on the Ru metal cap layer and on the first dielectric layer, etching a recessed feature in the second dielectric layer to expose the Ru metal cap layer, and performing a cleaning process that removes polymer etch residue from the Ru metal cap layer in the recessed feature.

Abstract: Embodiments of methods for patterning using enhancement of surface adhesion are presented. In an embodiment, a method for patterning using enhancement of surface adhesion may include providing an input substrate with an anti-reflective coating layer and an underlying layer. Such a method may also include performing a surface adhesion modification process on the substrate, the surface adhesion modification process utilizing a plasma treatment configured to increase an adhesion property of an anti-reflective coating layer without affecting downstream processes. In an embodiment, the method may also include performing a photoresist coating process, a mask exposure process, and a developing process to generate a target patterned structure in a photoresist layer on the substrate. In such embodiments, the method may include controlling operating parameters of the surface adhesion modification process to achieve target profiles of the patterned structure and substrate throughput objectives.

Abstract: A system and method for performing location specific processing of a workpiece is described. The method includes placing a microelectronic workpiece in a beam processing system, selecting a beam scan size for a beam scan pattern that is smaller than a dimension of the microelectronic workpiece, generating a processing beam, and processing a target region of the microelectronic workpiece by irradiating the processing beam along the beam scan pattern onto the target region within the beam scan size selected for processing the microelectronic workpiece.

Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.

Abstract: A substrate processing method for forming a self-aligned contact using selective SiO2 deposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiO2 layer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.

Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

Abstract: A method for correcting a surface profile on a substrate is described. In particular, the method includes receiving a substrate having a heterogeneous layer composed of a first material and a second material, wherein the heterogeneous layer has an initial upper surface exposing the first material and the second material, and defining a first surface profile across the substrate. The method further includes setting a target surface profile for the heterogeneous layer, selectively removing at least a portion of the first material using a gas cluster ion beam (GCIB) etching process, and recessing the first material beneath the second material, and thereafter, selectively removing at least a portion of the second material to achieve a final upper surface exposing the first material and the second material, and defining a second surface profile, wherein the second surface profile is within a pre-determined tolerance of the target surface profile.

Abstract: A system and method for performing location specific processing of a workpiece is described. The method includes placing a microelectronic workpiece in a beam processing system, selecting a beam scan size for a beam scan pattern that is smaller than a dimension of the microelectronic workpiece, generating a processing beam, and processing a target region of the microelectronic workpiece by irradiating the processing beam along the beam scan pattern onto the target region within the beam scan size selected for processing the microelectronic workpiece.

Abstract: A method for patterning a substrate is described. The method includes receiving a substrate having a patterned layer, wherein the patterned layer defines a first mandrel pattern, and wherein a first material layer of a first composition is conformally deposited over the first mandrel pattern. The method further includes partially removing the first material layer using a first gas cluster ion beam (GCIB) etching process to expose a top surface of the first mandrel pattern, open a portion of the first material layer at a bottom region adjacent a feature of the first mandrel pattern, and retain a remaining portion of the first material layer on sidewalls of the first mandrel pattern; and selectively removing the first mandrel pattern using one or more etching processes to leave a second mandrel pattern comprising the remaining portion of the first material layer that remained on the sidewalls of the first mandrel pattern.