Abstract: A method for correcting a surface profile on a substrate is described. In particular, the method includes receiving a substrate having a heterogeneous layer composed of a first material and a second material, wherein the heterogeneous layer has an initial upper surface exposing the first material and the second material, and defining a first surface profile across the substrate. The method further includes setting a target surface profile for the heterogeneous layer, selectively removing at least a portion of the first material using a gas cluster ion beam (GCIB) etching process, and recessing the first material beneath the second material, and thereafter, selectively removing at least a portion of the second material to achieve a final upper surface exposing the first material and the second material, and defining a second surface profile, wherein the second surface profile is within a pre-determined tolerance of the target surface profile.

Abstract: A method for patterning a substrate is described. The method includes receiving a substrate having a patterned layer, wherein the patterned layer defines a first mandrel pattern, and wherein a first material layer of a first composition is conformally deposited over the first mandrel pattern. The method further includes partially removing the first material layer using a first gas cluster ion beam (GCIB) etching process to expose a top surface of the first mandrel pattern, open a portion of the first material layer at a bottom region adjacent a feature of the first mandrel pattern, and retain a remaining portion of the first material layer on sidewalls of the first mandrel pattern; and selectively removing the first mandrel pattern using one or more etching processes to leave a second mandrel pattern comprising the remaining portion of the first material layer that remained on the sidewalls of the first mandrel pattern.

Abstract: A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film.

Abstract: A method of modifying an upper layer of a workpiece using a gas cluster ion beam (GCIB) is described. The method includes collecting parametric data relating to an upper layer of a workpiece, and determining a predicted systematic error response for applying a GCIB to the upper layer to alter an initial profile of a measured attribute by using the parametric data. Additionally, the method includes identifying a target profile of the measured attribute, directing the GCIB toward the upper layer of the workpiece, and spatially modulating an applied property of the GCIB, based at least in part on the predicted systematic error response and the parametric data, as a function of position on the upper layer of the workpiece to achieve the target profile of the measured attribute.

Abstract: A method of modifying an upper layer of a workpiece using a gas cluster ion beam (GCIB) is described. The method includes collecting parametric data relating to an upper layer of a workpiece, and determining a predicted systematic error response for applying a GCIB to the upper layer to alter an initial profile of a measured attribute by using the parametric data. Additionally, the method includes identifying a target profile of the measured attribute, directing the GCIB toward the upper layer of the workpiece, and spatially modulating an applied property of the GCIB, based at least in part on the predicted systematic error response and the parametric data, as a function of position on the upper layer of the workpiece to achieve the target profile of the measured attribute.

Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.

Abstract: A non-volatile memory device is provided wherein a lower molding layer is formed on a substrate; a first horizontal interconnection is formed on the lower molding layer; an upper molding layer is formed on the first horizontal interconnection; a pillar is formed connected to the substrate by vertically passing through the upper molding layer, the first horizontal interconnection and the lower molding layer. The pillar has a lower part and an upper part, wherein the lower part is disposed on the same level as the first horizontal interconnection and has a first width and the upper part is disposed on a higher level than the first horizontal interconnection and has a second width different from the first width.

Abstract: A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film.

Abstract: A non-volatile memory device is provided wherein a lower molding layer is formed on a substrate; a first horizontal interconnection is formed on the lower molding layer; an upper molding layer is formed on the first horizontal interconnection; a pillar is formed connected to the substrate by vertically passing through the upper molding layer, the first horizontal interconnection and the lower molding layer. The pillar has a lower part and an upper part, wherein the lower part is disposed on the same level as the first horizontal interconnection and has a first width and the upper part is disposed on a higher level than the first horizontal interconnection and has a second width different from the first width.

Abstract: A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities areas, and a stacked material formed on the channel for data storage. The stacked material for data storage is formed by sequentially stacking a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer.

Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.

Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

Abstract: An electro-mechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.

Abstract: Methods of forming non-volatile memory devices include forming a semiconductor layer having a first impurity region of first conductivity type extending adjacent a first side thereof and a second impurity region of second conductivity type extending adjacent a second side thereof, on a substrate. A first electrically conductive layer is also provided, which is electrically coupled to the first impurity region. The semiconductor layer is converted into a plurality of semiconductor diodes having respective first terminals electrically coupled to the first electrically conductive layer. The first electrically conductive layer operates as a word line or bit line of the non-volatile memory device. The converting may include patterning the first impurity region into a plurality of cathodes or anodes of the plurality of semiconductor diodes (e.g., P-i-N diodes).

Abstract: An electromechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.

Abstract: Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.

Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

Abstract: In a thin film semiconductor device realized on a flexible substrate, an electronic device using the same, and a manufacturing method thereof, the thin film semiconductor device and an electronic device include a flexible substrate, a semiconductor chip, which is formed on the flexible substrate, and a protective cap, which seals the semiconductor chip. Durability of the thin film semiconductor device against stress due to bending of the substrate is improved by using the protective cap.

Abstract: A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.