Patents by Inventor Soo Jeon

Soo Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device having fuse circuits and method of controlling the same
    Patent number: 7738309
    Abstract: A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Jeon, Dae-Han Kim
  • Method of manufacturing semiconductor device with dual gates
    Patent number: 7727841
    Abstract: In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: June 1, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Lan Lee, Hag-Ju Cho, Taek-Soo Jeon, Yu-Gyun Shin, Sang-Bom Kang
  • Flash memory device and method of testing a flash memory device
    Patent number: 7710788
    Abstract: A flash memory device includes a flash fuse cell array, a trim code processing unit, a flash memory array, and a regulator. The fuse cell array, which includes multiple nonvolatile fuse cells, is configured to store a first trim code. The trim code processor is configured to generate a second trim code based on the first trim code provided by the fuse cell array and a voltage control code. The flash memory array includes multiple flash memory cells. The regulator is configured to generate a high voltage in response to the second trim code and to provide the high voltage to the flash memory array. The high voltage varies according to erase, program and read operations of the flash memory cells.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Jeon, Dae-Han Kim
  • MISSION SCHEDULING METHOD
    Publication number: 20100030606
    Abstract: Provided is a mission scheduling method. The mission scheduling method includes: when a time window representing a time range that a plurality of missions are executed and a duration of the missions are given, determining an execution start time and finish time of each of the missions; selecting a first mission that is first finished among the missions; selecting second missions which collide or do not collide with the first mission depending on the execution order of the second missions; and including in a schedule a mission that is first finished when the first mission and the second missions are respectively executed according to a combination of orders, wherein the first mission and the second missions according to the combination of orders do not collide with each other.
    Type: Application
    Filed: January 30, 2009
    Publication date: February 4, 2010
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Soo Jeon Lee, Won Chan Jung, Jae Hoon Kim
  • Bitline bias circuit and nor flash memory device including the bitline bias circuit
    Patent number: 7656714
    Abstract: The NOR flash memory device according to the present invention is operated by a high voltage supplied from bitline selection transistors and includes a bitline bias circuit for supplying a bias voltage of a constant level to the bitline bias transistor. In accordance with the present invention, it is possible to stably supply a desired voltage closing to a power voltage to the bitline bias transistor.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: February 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Jeon, Seung-Keun Lee
  • System and method for automatically operating UPFC (unified power flow controller) connected to SCADA (supervisory control and data acquisition)
    Patent number: 7642757
    Abstract: A system and method for operating a Unified Power Flow Controller (UPFC) connected to a SCADA (Supervisory Control and Data Acquisition) are disclosed. The UPFC automatic operation system receives power system data from the SCADA system, automatically determines UPFC's optimum operation conditions according to power system states. The system includes: a UPFC acting as a serial/parallel FACTS to control variables of a power system; a SCADA for periodically acquiring line data of the power system and state data of the UPFC; and an upper controller for analyzing data received from the SCADA, and determining an UPFC's optimum operation mode for each power system condition and UPFC's optimum set-point control commands.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: January 5, 2010
    Assignee: Korea Electric Power Corporation
    Inventors: Jong-Soo Yoon, Seung-Pil Moon, Won-Kyo Lee, Chang-Gon Kim, Jin-Boo Choo, Young-Cheul Choi, Young-Soo Jeon, Byung-Hoon Chang, Soo-Yeol Kim
  • VOLTAGE GENERATION CIRCUIT AND FLASH MEMORY DEVICE INCLUDING THE SAME
    Publication number: 20090284308
    Abstract: A voltage generation circuit includes a high voltage detector (HVD), a clock signal control unit (CSCU), an oscillator, a pumping clock control unit (PCCU), and a charge pump. The HVD compares a high voltage applied to a memory cell array with at least one reference voltage to provide at least one comparison signal. The CSCU provides a clock control signal for changing a frequency of a clock signal in response to the at least one comparison signal. The oscillator generates the clock signal having a frequency according to the clock control signal. The PCCU passes or intercepts the clock signal to provide a pumping clock signal, in response to a control signal. The charge pump consecutively performs charge pumping operations to provide the high voltage while the pumping clock signal is applied to the charge pump.
    Type: Application
    Filed: May 13, 2009
    Publication date: November 19, 2009
    Inventor: Hong-Soo Jeon
  • METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING TRANSISTORS WITH DIFFERENT GATE STRUCTURES
    Publication number: 20090253256
    Abstract: A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.
    Type: Application
    Filed: April 13, 2009
    Publication date: October 8, 2009
    Inventors: Hye-Lan Lee, Yu-Gyun Shin, Sang-Bom Kang, Hag-Ju Cho, Seong-Geon Park, Taek-Soo Jeon
  • METHOD FOR PREPARING A POLISHING SLURRY HAVING HIGH DISPERSION STABILITY
    Publication number: 20090229189
    Abstract: The present invention relates to an improved method for preparing a polishing slurry, comprising dispersing polishing particles and an anionic polymeric acid in water and then adding to the resulting dispersion an alkaline material in an amount of 0.1 to 8 weight parts based on 100 weight parts of the polishing particles. The polishing slurry obtained by the inventive method exhibits good dispersion stability and non-Prestonian polishing performance, which can be beneficially employed in chemical mechanical polishing of various precision electronic devices.
    Type: Application
    Filed: May 13, 2009
    Publication date: September 17, 2009
    Inventors: Yun Ju CHO, In Yeon LEE, Hoon Soo JEON, Duk Young HONG, Taiyoung KIM, Sangick LEE, Eunkyoung PARK
  • Non-volatile memory device and method of forming the same
    Publication number: 20090134448
    Abstract: Example embodiments provide a non-volatile semiconductor memory device and method of forming the same. The non-volatile memory device may include a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a first blocking insulation layer on the charge storage layer, and a gate electrode on the first blocking insulation layer, wherein the gate electrode includes aluminum and the first blocking insulation layer does not include aluminum.
    Type: Application
    Filed: September 5, 2008
    Publication date: May 28, 2009
    Inventors: Taek-Soo Jeon, Si-Young Choi, In-Sang Jeon, Sang-Bom Kang, Si-Hyung Lee, Seung-Hoon Hong
  • Semiconductor devices having transistors with different gate structures and methods of fabricating the same
    Patent number: 7531881
    Abstract: A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Lan Lee, Yu-Gyun Shin, Sang-Bom Kang, Hag-Ju Cho, Seong-Geon Park, Taek-Soo Jeon
  • Semiconductor device having metal gate patterns and related method of manufacture
    Patent number: 7494859
    Abstract: A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: February 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hag-Ju Cho, Taek-Soo Jeon, Hye-Lan Lee, Sang-Bom Kang, Yu-Gyun Shin
  • Flash memory device and voltage generating circuit for the same
    Patent number: 7486573
    Abstract: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: February 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Jeon, Dae-Han Kim
  • Method for Transmitting File Based on Multiplex Forwarder
    Publication number: 20080288592
    Abstract: Provided is a method for transmitting a file based on a multiplex forwarder using a session join time interval. The method includes the steps of: a) transmitting a session join request message to a source and joining to a corresponding session; b) when a member joins the session, transmitting a forwarder candidate list request message to the source and receiving a forwarder candidate list; c) skipping a specific member among members on the transmitted forwarder candidate list; and d) transmitting a forwarder request message to the members on the forwarder candidate list excluding the specific member, selecting a member permitting the request as a forwarder, and receiving a gift, which is a packet, from the selected forwarder.
    Type: Application
    Filed: November 21, 2006
    Publication date: November 20, 2008
    Inventors: Soo-Jeon Lee, Jae-Hoon Kim
  • Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed
    Patent number: 7399670
    Abstract: A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: July 15, 2008
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Taek-Soo Jeon, Yu-Gyun Shin, Sang-Bom Kang, Hong-Bae Park, Hag-Ju Cho, Hye-Lan Lee, Beom-Jun Jin, Seong-Geon Park
  • SEMICONDUCTOR MEMORY DEVICE HAVING FUSE CIRCUITS AND METHOD OF CONTROLLING THE SAME
    Publication number: 20080158977
    Abstract: A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.
    Type: Application
    Filed: November 28, 2007
    Publication date: July 3, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-Soo Jeon, Dae-Han Kim
  • Plasma display panel with improved barrier rib structure
    Patent number: 7391155
    Abstract: A plasma display panel having barrier ribs designed to prevent phosphor material from forming on a top surface thereof. The barrier ribs include a plurality of parallel first barrier rib members and a plurality of parallel second barrier rib members formed substantially perpendicularly intersecting the first barrier rib members. The first barrier rib members have a cross-sectional apex width and the second barrier rib members have a cross-sectional apex. The apex width of the first barrier rib members is less than the apex width of the second barrier rib members, so that when the phosphor material is deposited thereon, the phosphor accumulates on the sidewalls of the barrier ribs and between the barrier ribs, and not on top of the barrier ribs, thus improving image quality.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 24, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Byung-Soo Jeon
  • Washing machine
    Patent number: D597712
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: August 4, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Soo Jeon, Sang Ho Park, Jeong Min Kim
  • Washing machine
    Patent number: D599508
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: September 1, 2009
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Hyoung Sub Choi, Gyoo Sang Choi, Sang Ho Park, Jeong Min Kim, Chan Young Lee, Dong Won Chun, Jong Soo Jeon
  • Washing machine
    Patent number: D599509
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: September 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Soo Jeon, Sang Ho Park, Jeong Min Kim