Patents by Inventor Soo-Jin Chua

Soo-Jin Chua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901186
    Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: February 13, 2024
    Assignees: Massachusetts Institute of Technology, Nanyang Technological University, National University of Singapore
    Inventors: Li Zhang, Kwang Hong Lee, Keith Cheng Yeow Ng, Kenneth Eng Kian Lee, Eugene A. Fitzgerald, Soo Jin Chua, Chuan Seng Tan
  • Patent number: 11087674
    Abstract: Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: August 10, 2021
    Assignees: Nanyang Technological University, Massachusetts Institute of Technology, National University of Singapore
    Inventors: Joseph Sylvester Chang, Wei Shu, Yong Qu, Eugene A. Fitzgerald, Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Siau Ben Chiah
  • Publication number: 20200388501
    Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.
    Type: Application
    Filed: February 19, 2019
    Publication date: December 10, 2020
    Applicants: Massachusetts Institute of Technology, Nanyang Technological University, National University of Singapore
    Inventors: Li Zhang, Kwang Hong Lee, Keith Cheng Yeow Ng, Kenneth Eng Kian Lee, Eugene A. Fitzgerald, Soo Jin Chua, Chuan Seng Tan
  • Patent number: 10847553
    Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignees: Massachusetts Institute of Technology, Nanyang Technological University, National University of Singapore
    Inventors: Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Eugene A. Fitzgerald, Siau Ben Chiah, Joseph Sylvester Chang, Yong Qu, Wei Shu, Kwang Hong Lee, Bing Wang
  • Patent number: 10672608
    Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 2, 2020
    Assignees: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological University
    Inventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
  • Publication number: 20190392755
    Abstract: Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.
    Type: Application
    Filed: February 1, 2018
    Publication date: December 26, 2019
    Applicants: Nanyang Technological University, Massachusetts Institute of Technology, National University of Singapore
    Inventors: Joseph Sylvester Chang, Wei Shu, Yong Qu, Eugene A. Fitzgerald, Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Siau Ben Chiah
  • Publication number: 20190355766
    Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.
    Type: Application
    Filed: January 12, 2018
    Publication date: November 21, 2019
    Inventors: Li ZHANG, Eng Kian, Kenneth LEE, Soo Jin CHUA, Eugene A. FITZGERALD, Siau Ben CHIAH, Joseph Sylvester CHANG, Yong QU, Wei SHU, Kwang Hong LEE, Bing WANG
  • Patent number: 10324256
    Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: June 18, 2019
    Assignees: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological University
    Inventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
  • Publication number: 20190051516
    Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.
    Type: Application
    Filed: January 20, 2017
    Publication date: February 14, 2019
    Inventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
  • Publication number: 20190035628
    Abstract: Method and structure for reducing substrate fragility. In one embodiment, a substrate for metamorphic epitaxy of a material film is provided, the substrate comprising a passivation layer defining a growth window for the material film on a deposition surface of the substrate, the growth window being laterally spaced from an edge of the substrate.
    Type: Application
    Filed: January 19, 2017
    Publication date: January 31, 2019
    Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NATIONAL UNIVERSITY OF SINGAPORE, NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Li ZHANG, Kwang Hong LEE, Shuyu BAO, Eng Kian Kenneth LEE, Eugene A. FITZGERALD, Soo Jin CHUA, Chuan Seng TAN
  • Patent number: 10103359
    Abstract: The present invention refers to a multilayer barrier film capable of encapsulating a moisture and/or oxygen sensitive electronic or optoelectronic device, the barrier film comprises at least one nanostructured layer comprising reactive nanoparticles capable of interacting with moisture and/or oxygen, the reactive nanoparticles being distributed within a polymeric binder, and at least one ultraviolet light neutralizing layer comprising a material capable of absorbing ultraviolet light, thereby limiting the transmission of ultraviolet light through the barrier film.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: October 16, 2018
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Senthil Kumar Ramadas, Soo Jin Chua, Lin Karen Ke
  • Publication number: 20180172903
    Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 21, 2018
    Applicants: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological University
    Inventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
  • Patent number: 9874689
    Abstract: A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: January 23, 2018
    Assignees: National University of Singapore, Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
  • Patent number: 9799854
    Abstract: The present invention relates to a multilayer barrier film capable of encapsulating a moisture and/or oxygen sensitive electronic or optoelectronic device, the barrier film including at least one nanostructured layer including reactive nanoparticles capable of interacting with moisture and/or oxygen, the reactive nanoparticles being distributed within a polymeric binder, and at least one ultraviolet light neutralizing layer comprising a material capable of absorbing ultraviolet light, thereby limiting the transmission of ultraviolet light through the barrier film.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: October 24, 2017
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Senthil Kumar Ramadas, Soo Jin Chua, Lin Karen Ke
  • Publication number: 20170098799
    Abstract: A barrier stack for encapsulating a moisture and/or oxygen sensitive electronic device is provided. The barrier stack comprises a multilayer film having at least one barrier layer having low moisture and/or oxygen permeability, and at least one sealing layer arranged to be in contact with a surface of the barrier layer, wherein the sealing material comprises reactive nanoparticles capable of interacting with moisture and/or oxygen, thereby retarding the permeation of moisture and/or oxygen through defects present in the barrier layer.
    Type: Application
    Filed: October 7, 2016
    Publication date: April 6, 2017
    Inventors: Senthil Kumar RAMADAS, Soo Jin CHUA
  • Patent number: 9493348
    Abstract: A barrier stack for encapsulating a moisture and/or oxygen sensitive electronic device is provided. The barrier stack comprises a multilayer film having at least one barrier layer having low moisture and/or oxygen permeability, and at least one sealing layer arranged to be in contact with a surface of the barrier layer, wherein the sealing material comprises reactive nanoparticles capable of interacting with moisture and/or oxygen, thereby retarding the permeation of moisture and/or oxygen through defects present in the barrier layer.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: November 15, 2016
    Assignee: Agency for Science, Technology and Research
    Inventors: Senthil Kumar Ramadas, Soo Jin Chua
  • Publication number: 20160327737
    Abstract: A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.
    Type: Application
    Filed: January 14, 2015
    Publication date: November 10, 2016
    Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, National University of Singapore, Nanyang Technological University
    Inventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
  • Patent number: 9011705
    Abstract: The present invention relates to a method of forming polymer substrate with variable refractive index sensitivity, the method comprising the steps of: (a) contacting a metal-coated patterned mold with a polymer substrate at a temperature sufficient to deform said polymer substrate to thereby deposit a patterned mask of a metal film on the polymer substrate; and (b) etching away portions of said polymer substrate not covered by said patterned mask under conditions to form a region of variable refractive index sensitivity on said polymer substrate.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: April 21, 2015
    Assignee: Agency for Science, Technology and Research
    Inventors: Kwok Wei Shah, Xiaodi Su, Soo Jin Chua, Hong Yee Low
  • Patent number: 8915121
    Abstract: An encapsulated device comprising an integrated gas permeation sensor is provided, comprising a base substrate with an electronic component arranged thereon being enclosed within an encapsulation for protecting the electronic component from moisture and/or oxygen; at least one sensor is arranged within the encapsulation to measure the permeation of gas into the encapsulation; each sensor comprises an electrically conductive sensing element comprising a moisture and/or oxygen sensitive material, wherein the reaction of said material with moisture and/or oxygen results in a change in the electrical resistance/conductivity of the sensor.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: December 23, 2014
    Assignee: Agency for Science, Technology and Research
    Inventors: Ramadas Senthil Kumar, Adrian Paul Burden, Soo Jin Chua
  • Patent number: 8859399
    Abstract: A method of at least partially releasing an epitaxial layer of a material from a substrate. The method comprises the steps of: forming a patterned sacrificial layer on the substrate such that the substrate is partially exposed and partially covered by the sacrificial layer; growing the epitaxial layer on the patterned sacrificial layer by nano-epitaxial lateral overgrowth such that the epitaxial layer is formed above an intermediate layer comprising the patterned sacrificial layer and said material; and selectively etching the patterned sacrificial layer such that the epitaxial layer is at least partially released from the substrate.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: October 14, 2014
    Assignee: Agency for Science, Technology and Research
    Inventors: Keyan Zang, Jinghua Teng, Soo Jin Chua