Patents by Inventor Soo-Jin Chua
Soo-Jin Chua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901186Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.Type: GrantFiled: February 19, 2019Date of Patent: February 13, 2024Assignees: Massachusetts Institute of Technology, Nanyang Technological University, National University of SingaporeInventors: Li Zhang, Kwang Hong Lee, Keith Cheng Yeow Ng, Kenneth Eng Kian Lee, Eugene A. Fitzgerald, Soo Jin Chua, Chuan Seng Tan
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Patent number: 11087674Abstract: Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.Type: GrantFiled: February 1, 2018Date of Patent: August 10, 2021Assignees: Nanyang Technological University, Massachusetts Institute of Technology, National University of SingaporeInventors: Joseph Sylvester Chang, Wei Shu, Yong Qu, Eugene A. Fitzgerald, Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Siau Ben Chiah
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Publication number: 20200388501Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.Type: ApplicationFiled: February 19, 2019Publication date: December 10, 2020Applicants: Massachusetts Institute of Technology, Nanyang Technological University, National University of SingaporeInventors: Li Zhang, Kwang Hong Lee, Keith Cheng Yeow Ng, Kenneth Eng Kian Lee, Eugene A. Fitzgerald, Soo Jin Chua, Chuan Seng Tan
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Patent number: 10847553Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.Type: GrantFiled: January 12, 2018Date of Patent: November 24, 2020Assignees: Massachusetts Institute of Technology, Nanyang Technological University, National University of SingaporeInventors: Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Eugene A. Fitzgerald, Siau Ben Chiah, Joseph Sylvester Chang, Yong Qu, Wei Shu, Kwang Hong Lee, Bing Wang
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Patent number: 10672608Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.Type: GrantFiled: January 20, 2017Date of Patent: June 2, 2020Assignees: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological UniversityInventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
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Publication number: 20190392755Abstract: Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.Type: ApplicationFiled: February 1, 2018Publication date: December 26, 2019Applicants: Nanyang Technological University, Massachusetts Institute of Technology, National University of SingaporeInventors: Joseph Sylvester Chang, Wei Shu, Yong Qu, Eugene A. Fitzgerald, Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Siau Ben Chiah
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Publication number: 20190355766Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.Type: ApplicationFiled: January 12, 2018Publication date: November 21, 2019Inventors: Li ZHANG, Eng Kian, Kenneth LEE, Soo Jin CHUA, Eugene A. FITZGERALD, Siau Ben CHIAH, Joseph Sylvester CHANG, Yong QU, Wei SHU, Kwang Hong LEE, Bing WANG
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Patent number: 10324256Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: GrantFiled: December 11, 2017Date of Patent: June 18, 2019Assignees: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological UniversityInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
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Publication number: 20190051516Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.Type: ApplicationFiled: January 20, 2017Publication date: February 14, 2019Inventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
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Publication number: 20190035628Abstract: Method and structure for reducing substrate fragility. In one embodiment, a substrate for metamorphic epitaxy of a material film is provided, the substrate comprising a passivation layer defining a growth window for the material film on a deposition surface of the substrate, the growth window being laterally spaced from an edge of the substrate.Type: ApplicationFiled: January 19, 2017Publication date: January 31, 2019Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NATIONAL UNIVERSITY OF SINGAPORE, NANYANG TECHNOLOGICAL UNIVERSITYInventors: Li ZHANG, Kwang Hong LEE, Shuyu BAO, Eng Kian Kenneth LEE, Eugene A. FITZGERALD, Soo Jin CHUA, Chuan Seng TAN
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Patent number: 10103359Abstract: The present invention refers to a multilayer barrier film capable of encapsulating a moisture and/or oxygen sensitive electronic or optoelectronic device, the barrier film comprises at least one nanostructured layer comprising reactive nanoparticles capable of interacting with moisture and/or oxygen, the reactive nanoparticles being distributed within a polymeric binder, and at least one ultraviolet light neutralizing layer comprising a material capable of absorbing ultraviolet light, thereby limiting the transmission of ultraviolet light through the barrier film.Type: GrantFiled: April 8, 2009Date of Patent: October 16, 2018Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Senthil Kumar Ramadas, Soo Jin Chua, Lin Karen Ke
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Publication number: 20180172903Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: ApplicationFiled: December 11, 2017Publication date: June 21, 2018Applicants: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological UniversityInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
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Patent number: 9874689Abstract: A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: GrantFiled: January 14, 2015Date of Patent: January 23, 2018Assignees: National University of Singapore, Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
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Patent number: 9799854Abstract: The present invention relates to a multilayer barrier film capable of encapsulating a moisture and/or oxygen sensitive electronic or optoelectronic device, the barrier film including at least one nanostructured layer including reactive nanoparticles capable of interacting with moisture and/or oxygen, the reactive nanoparticles being distributed within a polymeric binder, and at least one ultraviolet light neutralizing layer comprising a material capable of absorbing ultraviolet light, thereby limiting the transmission of ultraviolet light through the barrier film.Type: GrantFiled: December 13, 2013Date of Patent: October 24, 2017Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Senthil Kumar Ramadas, Soo Jin Chua, Lin Karen Ke
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Publication number: 20170098799Abstract: A barrier stack for encapsulating a moisture and/or oxygen sensitive electronic device is provided. The barrier stack comprises a multilayer film having at least one barrier layer having low moisture and/or oxygen permeability, and at least one sealing layer arranged to be in contact with a surface of the barrier layer, wherein the sealing material comprises reactive nanoparticles capable of interacting with moisture and/or oxygen, thereby retarding the permeation of moisture and/or oxygen through defects present in the barrier layer.Type: ApplicationFiled: October 7, 2016Publication date: April 6, 2017Inventors: Senthil Kumar RAMADAS, Soo Jin CHUA
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Patent number: 9493348Abstract: A barrier stack for encapsulating a moisture and/or oxygen sensitive electronic device is provided. The barrier stack comprises a multilayer film having at least one barrier layer having low moisture and/or oxygen permeability, and at least one sealing layer arranged to be in contact with a surface of the barrier layer, wherein the sealing material comprises reactive nanoparticles capable of interacting with moisture and/or oxygen, thereby retarding the permeation of moisture and/or oxygen through defects present in the barrier layer.Type: GrantFiled: November 6, 2006Date of Patent: November 15, 2016Assignee: Agency for Science, Technology and ResearchInventors: Senthil Kumar Ramadas, Soo Jin Chua
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Publication number: 20160327737Abstract: A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: ApplicationFiled: January 14, 2015Publication date: November 10, 2016Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, National University of Singapore, Nanyang Technological UniversityInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
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Patent number: 9011705Abstract: The present invention relates to a method of forming polymer substrate with variable refractive index sensitivity, the method comprising the steps of: (a) contacting a metal-coated patterned mold with a polymer substrate at a temperature sufficient to deform said polymer substrate to thereby deposit a patterned mask of a metal film on the polymer substrate; and (b) etching away portions of said polymer substrate not covered by said patterned mask under conditions to form a region of variable refractive index sensitivity on said polymer substrate.Type: GrantFiled: July 26, 2012Date of Patent: April 21, 2015Assignee: Agency for Science, Technology and ResearchInventors: Kwok Wei Shah, Xiaodi Su, Soo Jin Chua, Hong Yee Low
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Patent number: 8915121Abstract: An encapsulated device comprising an integrated gas permeation sensor is provided, comprising a base substrate with an electronic component arranged thereon being enclosed within an encapsulation for protecting the electronic component from moisture and/or oxygen; at least one sensor is arranged within the encapsulation to measure the permeation of gas into the encapsulation; each sensor comprises an electrically conductive sensing element comprising a moisture and/or oxygen sensitive material, wherein the reaction of said material with moisture and/or oxygen results in a change in the electrical resistance/conductivity of the sensor.Type: GrantFiled: December 28, 2006Date of Patent: December 23, 2014Assignee: Agency for Science, Technology and ResearchInventors: Ramadas Senthil Kumar, Adrian Paul Burden, Soo Jin Chua
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Patent number: 8859399Abstract: A method of at least partially releasing an epitaxial layer of a material from a substrate. The method comprises the steps of: forming a patterned sacrificial layer on the substrate such that the substrate is partially exposed and partially covered by the sacrificial layer; growing the epitaxial layer on the patterned sacrificial layer by nano-epitaxial lateral overgrowth such that the epitaxial layer is formed above an intermediate layer comprising the patterned sacrificial layer and said material; and selectively etching the patterned sacrificial layer such that the epitaxial layer is at least partially released from the substrate.Type: GrantFiled: November 19, 2009Date of Patent: October 14, 2014Assignee: Agency for Science, Technology and ResearchInventors: Keyan Zang, Jinghua Teng, Soo Jin Chua