Patents by Inventor Soo-Jin Chua

Soo-Jin Chua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7910937
    Abstract: A method and structure for fabricating III-V nitride layers on silicon substrates includes a substrate, a transition structure having AlGaN, AlN and GaN layers, and a superlattice structure having AlGaN and GaN layers. In the invention, the large lattice mismatch (17%) between GaN and silicon is solved by using AlN as the first buffer layer with a 5:4 coincidence between AlN(0001) and Si(111) lattice to reduce the lattice mismatch to 1.3%.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: March 22, 2011
    Assignee: Agency for Science, Technology and Research
    Inventors: Peng Chen, Soo Jin Chua, Zhonglin Miao, Sudhiranjan Tripathy
  • Publication number: 20100294024
    Abstract: An encapsulated device comprising an integrated gas permeation sensor is provided, comprising a base substrate with an electronic component arranged thereon being enclosed within an encapsulation for protecting the electronic component from moisture and/or oxygen; at least one sensor is arranged within the encapsulation to measure the permeation of gas into the encapsulation; each sensor comprises an electrically conductive sensing element comprising a moisture and/or oxygen sensitive material, wherein the reaction of said material with moisture and/or oxygen results in a change in the electrical resistance/conductivity of the sensor.
    Type: Application
    Filed: December 28, 2006
    Publication date: November 25, 2010
    Inventors: Ramadas Senthil Kumar, Adrian Paul Burden, Soo Jin Chua
  • Patent number: 7833425
    Abstract: A method of forming an array of selectively shaped optical elements on a substrate, the method including the steps of providing the substrate, the substrate having an optical layer placed thereon; placing a layer of particles on the optical layer; performing an etching cycle. The cycle includes the steps of: etching the layer of particles, using a first etching process so as to reduce the size of the particles within the layer, then; simultaneously etching the optical layer and the layer of particles, using a second etching process, the further reducing particles forming a mask over areas of the optical layer to create discrete optical elements from the optical layer.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: November 16, 2010
    Assignee: Agency for Science, Technology and Research
    Inventors: Benzhong Wang, Soo Jin Chua
  • Patent number: 7811846
    Abstract: A method for fabricating an array of semiconductor devices comprising the steps of providing a non-metallic substrate, placing a layer of spheres on said substrate, reducing diameter of the spheres, encapsulating the spheres in a matrix of rigid material, finishing an upper surface of said matrix to expose a portion of said spheres, removing the spheres to form an array of cavities within said matrix, and forming features in said cavities in contact with said substrate so as to form the device.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: October 12, 2010
    Assignee: Agency for Science, Technology and Research
    Inventors: Benzhong Wang, Soo Jin Chua
  • Publication number: 20100227437
    Abstract: A method for fabricating an array of semiconductor devices comprising the steps of providing a non-metallic substrate, placing a layer of spheres on said substrate, reducing diameter of the spheres, encapsulating the spheres in a matrix of rigid material, finishing an upper surface of said matrix to expose a portion of said spheres, removing the spheres to form an array of cavities within said matrix, and forming features in said cavities in contact with said substrate so as to form the device.
    Type: Application
    Filed: March 21, 2006
    Publication date: September 9, 2010
    Applicant: Agency for Science, Technology and Research
    Inventors: Benzhong Wang, Soo Jin Chua
  • Publication number: 20100224857
    Abstract: A multiple quantum well (MQW) structure for a light emitting diode and a method for fabricating a MQW structure for a light emitting diode are provided. The MQW structure comprises a plurality of quantum well structures, each quantum well structure comprising: a barrier layer; and a well layer having quantum dot nanostructures embedded therein formed on the barrier layer, the barrier and the well layer comprising a first metal-nitride based material; wherein at least one of the quantum well structures further comprises a capping layer formed on the well layer, the capping layer comprising a second metal-nitride based material having a different metal element compared to the first metal-nitride based material.
    Type: Application
    Filed: October 12, 2007
    Publication date: September 9, 2010
    Applicant: Agency for Science Tecnology and Research
    Inventors: Chew Beng Soh, Soo Jin Chua, Wei Liu, Jing Hua Teng
  • Publication number: 20100173483
    Abstract: The GaN single-crystal substrate 11 in accordance with the present invention has a polished surface subjected to heat treatment for at least 10 minutes at a substrate temperature of at least 1020° C. in a mixed gas atmosphere containing at least an NH3 gas. As a consequence, an atomic rearrangement is effected in the surface of the substrate 11 in which a large number of minute defects are formed by polishing, so as to flatten the surface of the substrate 11. Therefore, the surface of an epitaxial layer 12 formed on the substrate 11 can be made flat.
    Type: Application
    Filed: March 16, 2010
    Publication date: July 8, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Masaki Ueno, Eiryo Takasuka, Soo-Jin Chua, Peng Chen
  • Patent number: 7733008
    Abstract: An Organic Light Emitting Diode (OLED) which is adapted to inhibit the formation and growth of non-emissive areas known as “dark spots.” The OLED comprises an anode disposed on a substrate, a cathode, an electroluminescent (EL) layer disposed between the anode and the cathode and a hole transport layer disposed between the anode and the EL layer. The OLED has one or more dielectric organic barrier layers disposed between one or more of the OLED's layers. These barrier layers are made from an organic polymer and are adapted to resist permeation by oxygen and moisture and to inhibit metal migration.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: June 8, 2010
    Assignee: Agency for Science, Technology and Research
    Inventors: Lin Ke, Senthil Kumar Ramadas, Soo Jin Chua
  • Publication number: 20100089636
    Abstract: A barrier stack for encapsulating a moisture and/or oxygen sensitive electronic device is provided. The barrier stack comprises a multilayer film having at least one barrier layer having low moisture and/or oxygen permeability, and at least one sealing layer arranged to be in contact with a surface of the barrier layer, wherein the sealing material comprises reactive nanoparticles capable of interacting with moisture and/or oxygen, thereby retarding the permeation of moisture and/or oxygen through defects present in the barrier layer.
    Type: Application
    Filed: November 6, 2006
    Publication date: April 15, 2010
    Inventors: Senthil Kumar Ramadas, Soo Jin Chua
  • Patent number: 7674717
    Abstract: A method of fabricating a two dimensional nano-structure array of features comprising the steps of providing a substrate (10); forming an intermediate layer on said substrate (20), said intermediate layer having at least two selectively located regions (21, 22) of different uniform thickness; placing at least one layer of elements (30) over said intermediate layer, said elements placed in a close-packed arrangement forming an array of voids (33) between said elements; etching the intermediate layer through said voids, and so forming the array of features (51, 52) in said intermediate layer corresponding to the voids.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: March 9, 2010
    Assignee: Agency for Science, Technology and Research
    Inventors: Benzhong Wang, Soo Jin Chua
  • Publication number: 20100025653
    Abstract: A light emitting diode and a method of fabricating a light emitting diode, the diode has a first set of multiple quantum wells (MQWs), each of the MQWs of the first set comprising a wetting layer providing nucleation sites for quantum dots (QDs) or QD-like structures in a well layer of said each MQW; and a second set of MQWs, each of the MQWs of the second set formed so as to exhibit a photoluminescence (PL) peak wavelength shifted compared to the MQWs of the first set.
    Type: Application
    Filed: September 8, 2006
    Publication date: February 4, 2010
    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Chew Beng Soh, Soo Jin Chua, Haryono Hartono
  • Publication number: 20090302308
    Abstract: A white-light emitting diode comprises an n-type semiconductor layer, one or more quantum well structures formed over the n-type semiconductor layer, a p-type semiconductor layer formed on the quantum well structure, a first electrode formed on the p-type semiconductor, and a second electrode formed on at least a portion of the n-type semiconductor layer. Each quantum well structure includes an InxGa1-xN quantum well layer, an InyGa1-yN barrier layer (x>0.3 or x=0.3), and InzGa1-zN quantum dots, where x<y<z?1.
    Type: Application
    Filed: September 22, 2006
    Publication date: December 10, 2009
    Applicants: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH, SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Soo-Jin Chua, Peng Chen, Zhen Chen, Eiryo Takasuka
  • Patent number: 7598104
    Abstract: A method of forming a metal contact and passivation of a semiconductor feature, and devices made using the method. The method comprises the steps of forming a dielectric mask on a semiconductor substrate utilising photolithography processes; etching the semiconductor substrate such that one or more features are formed underneath respective portions of the dielectric mask; depositing a passivation layer on the substrate with the dielectric mask in place above the features; subjecting the substrate to an etchant such that the dielectric mask is etched at a higher rate than the passivation layer, whereby portions of the passivation layer deposited on the dielectric mask are lifted off from the substrate; and depositing a metal layer on the substrate including over the remaining passivation layer and exposed portions of the features.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: October 6, 2009
    Assignee: Agency for Science, Technology and Research
    Inventors: Jinghua Teng, Ee Leong Lim, Soo Jin Chua
  • Publication number: 20090206320
    Abstract: A white light-emitting diode is fabricated by metal organic chemical vapor deposition (MOCVD), which can produce a broad band emission covering all the visible range in the spectrum by capping the Indium nitride (InN) and Indium-rich Indium Gallium Nitride (InGaN) quantum dots (QDs) in single or multiple InxGa1-xN/InyGa1-yN quantum wells (QWs) by introducing bursts of at least one of Timethylindium (TMIn), Triethylindium (TEIn) and Ethyldimethylindium (EDMIn), which serve as nuclei for the growth of QDs in QWs. The diode can thus radiate white light ranging from 400 nm to 750 nm by adjusting the In burst parameters.
    Type: Application
    Filed: March 24, 2005
    Publication date: August 20, 2009
    Applicant: Agency for Science, Technology and Research
    Inventors: Soo Jin Chua, Peng Chen, Eiryo Takasuka
  • Publication number: 20090001416
    Abstract: Si-doped porous GaN is fabricated by UV-enhanced Pt-assisted electrochemical etching and together with a low-temperature grown buffer layer are utilized as the template for InGaN growth. The porous network in GaN shows nanostructures formed on the surface. Subsequent growth of InGaN shows that it is relaxed on these nanostructures as the area on which the growth takes place is very small. The strain relaxation favors higher indium incorporation. Besides, this porous network creates a relatively rough surface of GaN to modify the surface energy which can enhance the nucleation of impinging indium atoms thereby increasing indium incorporation. It shifts the luminescence from 445 nm for a conventionally grown InGaN structure to 575 nm and enhances the intensity by more than two-fold for the growth technique in the present invention under the same growth conditions. There is also a spectral broadening of the output extending from 480 nm to 720 nm.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Soo Jin Chua, Haryono Hartono, Chew Beng Soh
  • Publication number: 20080318003
    Abstract: A method for fabricating nano-structures comprising providing a substrate for the growth of the nano-structures; providing a template having predetermined nano-patterns; providing at least one layer of mask material between the template and the substrate; transferring the nano-patterns from the template to the layer of mask material; and growing the nano-structures on the substrate in areas exposed through the nano-patterns in the layer of mask material by a bottom-up growth process.
    Type: Application
    Filed: August 31, 2004
    Publication date: December 25, 2008
    Applicants: Agency for Science, Technology and Research, National University of Singapore
    Inventors: Soo Jin Chua, Peng Chen, Yadong Wang
  • Patent number: 7432533
    Abstract: An encapsulation for a device is disclosed. Spacer particles are randomly located in the device region to prevent a cap mounted on the substrate from contacting the active components, thereby protecting them from damage. The spacer particles comprise a base and an upper portion, the base being at least equal to or wider than the upper portion, for preventing the generation of dark spots around the spacer particles.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: October 7, 2008
    Assignees: Osram GmbH, Agency for Science, Technology and Research
    Inventors: Mark Auch, Ewald Guenther, Soo Jin Chua
  • Patent number: 7419842
    Abstract: A method of encapsulating a device is disclosed. Spacer particles are randomly located in a device region to prevent a cap mounted on the substrate from contacting the active components when pressure is applied to the cap, thereby protecting the active components from damage. The spacer particles comprise a base and an upper portion, the base being at least equal to or wider than the upper portion.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: September 2, 2008
    Assignees: Osram GmbH, Agency for Science, Technology and Research
    Inventors: Mark Auch, Ewald Guenther, Soo Jin Chua
  • Publication number: 20080121916
    Abstract: A method of forming a metal contact and passivation of a semiconductor feature, and devices made using the method. The method comprises the steps of forming a dielectric mask on a semiconductor substrate utilising photolithography processes; etching the semiconductor substrate such that one or more features are formed underneath respective portions of the dielectric mask; depositing a passivation layer on the substrate with the dielectric mask in place above the features; subjecting the substrate to an etchant such that the dielectric mask is etched at a higher rate than the passivation layer, whereby portions of the passivation layer deposited on the dielectric mask are lifted off from the substrate; and depositing a metal layer on the substrate including over the remaining passivation layer and exposed portions of the features.
    Type: Application
    Filed: November 13, 2007
    Publication date: May 29, 2008
    Applicant: Agency for Science, Technology and Research
    Inventors: Jinghua TENG, Ee Leong Lim, Soo Jin Chua
  • Publication number: 20080047929
    Abstract: A method of forming an array of selectively shaped optical elements on a substrate, the method including the steps of providing the substrate, the substrate having an optical layer placed thereon; placing a layer of particles on the optical layer; performing an etching cycle. The cycle includes the steps of: etching the layer of particles, using a first etching process so as to reduce the size of the particles within the layer, then; simultaneously etching the optical layer and the layer of particles, using a second etching process, the further reducing particles forming a mask over areas of the optical layer to create discrete optical elements from the optical layer.
    Type: Application
    Filed: August 22, 2007
    Publication date: February 28, 2008
    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Benzhong WANG, Soo Jin CHUA