Abstract: In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.

Abstract: Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO2) on a silicon (Si)-containing substrate. A reactive gas containing ammonia (NH3) gas is supplied to the preliminary insulating layer. Nitrogen radicals (N*) and hydrogen radicals (H*) are generated from the ammonia gas using plasma. The hydrogen radicals combine with oxygen of the preliminary insulating layer, and the nitrogen radicals combine with the silicon oxide so that an insulating layer including hydroxides (OH) and silicon oxynitride (SiON) can be formed.

Abstract: Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO2) on a silicon (Si)-containing substrate. A reactive gas containing ammonia (NH3) gas is supplied to the preliminary insulating layer. Nitrogen radicals (N*) and hydrogen radicals (H*) are generated from the ammonia gas using plasma. The hydrogen radicals combine with oxygen of the preliminary insulating layer, and the nitrogen radicals combine with the silicon oxide so that an insulating layer including hydroxides (OH) and silicon oxynitride (SiON) can be formed.

Abstract: In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.

Abstract: Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.

Abstract: A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region.

Abstract: A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.

Abstract: Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.

Abstract: A method of forming an oxide layer on a trench, a method of forming a semiconductor device, and a semiconductor device, the method of forming an oxide layer on a trench including forming a first trench in a first portion of a substrate and a second trench in a second portion of the substrate, the first portion being different from the second portion, performing a plasma doping process on at least one of the first portion and the second portion to implant an impurity therein, and performing an oxidation process to form an oxide layer on the substrate, a thickness of the oxide layer being determined by the impurity implanted in the substrate.

Abstract: A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region.

Abstract: Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.

Abstract: A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.

Abstract: A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.

Abstract: In plasma ion doping operations, a wafer is positioned on a susceptor within a reaction chamber and an ion doping source gas is plasmalyzed in an upper part of the reaction chamber above a major surface of the wafer while supplying a control gas into the reaction chamber in a lower part of the reaction chamber opposite the major surface of the wafer to thereby dope ions into the major surface of the wafer. The ion doping source gas may comprise at least one halide gas, and the control gas may comprise at least one depositing gas, such as a silane gas. In further embodiments, a diluent gas, such as an inert gas, may be supplied to the reaction chamber while supplying the ion doping source gas and the control gas. Related plasma ion doping apparatus are described.

Abstract: A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.

Abstract: The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.

Abstract: A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.

Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a gate spacer disposed on both sidewalls of the gate pattern, and a fixed charge layer disposed in the semiconductor substrate below the gate spacer. Elements generating fixed charges are injected into the fixed charge layer. A layer in which carriers induced by the fixed charge layer are accumulated is disposed below the fixed charge layer. The elements are segregated to a substrate of the semiconductor substrate from the inside of the semiconductor substrate by heat.

Abstract: A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.

Abstract: The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.