Patents by Inventor Soo-Jin Hong
Soo-Jin Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6756654Abstract: The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.Type: GrantFiled: August 9, 2002Date of Patent: June 29, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hwa Heo, Soo-Jin Hong
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Patent number: 6740955Abstract: A method of forming a trench device isolation structure, wherein, after forming a trench in a predetermined area of a semiconductor substrate, a lower isolation pattern, an upper liner pattern, and an upper isolation pattern are sequentially formed to fill the trench. A lower device isolation layer is formed on an entire surface of the semiconductor substrate, and then etched to form the lower isolation pattern so that a top surface of the lower isolation pattern is lower than a top surface of the semiconductor substrate. An upper liner layer and an upper device isolation layer are formed on the entire surface of the semiconductor substrate including the lower isolation pattern, and then etched to form the upper liner pattern. As a result, the upper liner pattern covers the top surface of the lower isolation pattern and surrounds the bottom and the sidewall of the upper isolation pattern.Type: GrantFiled: May 8, 2003Date of Patent: May 25, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Jin Hong, Jin-Hwa Heo
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Patent number: 6699799Abstract: A method of forming a semiconductor device includes a liner is conformally stacked on a semiconductor substrate before coating an SOG layer thereon, and then curing the SOG layer, preferably in an ambient of oxygen radicals formed at a temperature of 1000° C. or higher when oxygen and hydrogen are supplied. The oxygen radicals are preferably formed by irradiating ultraviolet rays to ozone or forming oxygen plasma. The SOG layer is preferably made of a polysilazane-based material that may promote a conversion of the SOG layer into a silicon oxide layer.Type: GrantFiled: April 30, 2002Date of Patent: March 2, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Ho Ahn, Soo-Jin Hong, Jung-Il Lee, Kyung-won Park
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Patent number: 6683354Abstract: A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.Type: GrantFiled: November 16, 2001Date of Patent: January 27, 2004Assignee: Samsung Electronics, Co., Ltd.Inventors: Jin-Hwa Heo, Soo-Jin Hong
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Patent number: 6624041Abstract: A method for forming a trench type isolation film comprises filling a trench with a composite film, flattening the resultant, and annealing the flattened resultant before a gate oxide film is formed. The annealing diffuses out any contaminant existing in an area near and/or contacting the trench on a surface between a semiconductor substrate and a pad oxide film. Therefore, it is possible to prevent the portion of the gate oxide film which is near the trench from becoming thinner than other portions. Accordingly, it is possible to prevent the characteristic of the gate oxide film from deteriorating. In particular, it is possible to prevent a break down voltage from being lowered.Type: GrantFiled: May 21, 1999Date of Patent: September 23, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-jin Hong, Moon-han Park
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Patent number: 6593207Abstract: A method of forming a trench device isolation structure, wherein, after forming a trench in a predetermined area of a semiconductor substrate, a lower isolation pattern, an upper liner pattern, and an upper isolation pattern are sequentially formed to fill the trench. A lower device isolation layer is formed on an entire surface of the semiconductor substrate, and then etched to form the lower isolation pattern so that a top surface of the lower isolation pattern is lower than a top surface of the semiconductor substrate. An upper liner layer and an upper device isolation layer are formed on the entire surface of the semiconductor substrate including the lower isolation pattern, and then etched to form the upper liner pattern. As a result, the upper liner pattern covers the top surface of the lower isolation pattern and surrounds the bottom and the sidewall of the upper isolation pattern.Type: GrantFiled: April 15, 2002Date of Patent: July 15, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Jin Hong, Jin-Hwa Heo
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Patent number: 6583025Abstract: A method of forming a trench isolation structure prevents a nitride liner from being over-etched, i.e., prevents the so-called dent phenomenon from occurring. An etching mask pattern is formed on a semiconductor substrate. A trench is formed in the substrate by using the etching mask pattern as an etching mask. A nitride liner, serving as an oxidation barrier layer, is formed at the sides and bottom of the trench, and is then annealed in a furnace to density the same. In a subsequent etching process, such as that used to remove the etching mask pattern, the densified nitride liner resists being etched. Accordingly, a trench isolation structure having a good profile is produced.Type: GrantFiled: May 3, 2001Date of Patent: June 24, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Soo-Jin Hong
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Patent number: 6566229Abstract: A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane ([SiH2NH]n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 Å from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.Type: GrantFiled: November 26, 2001Date of Patent: May 20, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Jin Hong, Moon-Han Park, Ju-Seon Goo, Jin-Hwa Heo, Hong-Gun Kim, Eun-Kee Hong
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Publication number: 20030030121Abstract: The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.Type: ApplicationFiled: August 9, 2002Publication date: February 13, 2003Inventors: Jin-Hwa Heo, Soo-Jin Hong
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Publication number: 20030013272Abstract: A method of forming a trench device isolation structure, wherein, after forming a trench in a predetermined area of a semiconductor substrate, a lower isolation pattern, an upper liner pattern, and an upper isolation pattern are sequentially formed to fill the trench. A lower device isolation layer is formed on an entire surface of the semiconductor substrate, and then etched to form the lower isolation pattern so that a top surface of the lower isolation pattern is lower than a top surface of the semiconductor substrate. An upper liner layer and an upper device isolation layer are formed on the entire surface of the semiconductor substrate including the lower isolation pattern, and then etched to form the upper liner pattern. As a result, the upper liner pattern covers the top surface of the lower isolation pattern and surrounds the bottom and the sidewall of the upper isolation pattern.Type: ApplicationFiled: April 15, 2002Publication date: January 16, 2003Inventors: Soo-Jin Hong, Jin-Hwa Heo
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Publication number: 20020168873Abstract: A method of forming a semiconductor device includes a liner is conformally stacked on a semiconductor substrate before coating an SOG layer thereon, and then curing the SOG layer, preferably in an ambient of oxygen radicals formed at a temperature of 1000° C. or higher when oxygen and hydrogen are supplied. The oxygen radicals are preferably formed by irradiating ultraviolet rays to ozone or forming oxygen plasma. The SOG layer is preferably made of a polysilazane-based material that may promote a conversion of the SOG layer into a silicon oxide layer.Type: ApplicationFiled: April 30, 2002Publication date: November 14, 2002Inventors: Dong-Ho Ahn, Soo-Jin Hong, Jung-Il Lee, Kyung-Won Park
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Publication number: 20020127817Abstract: A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.Type: ApplicationFiled: November 16, 2001Publication date: September 12, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Jin-Hwa Heo, Soo-Jin Hong
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Publication number: 20020123206Abstract: A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane ([SiH2NH]n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 Å from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.Type: ApplicationFiled: November 26, 2001Publication date: September 5, 2002Inventors: Soo-Jin Hong, Moon-Han Park, Ju-Seon Goo, Jin-Hwa Heo, Hong-Gun Kim, Eun-Kee Hong
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Publication number: 20020110994Abstract: A method for forming a trench type isolation film comprises filling a trench with a composite film, flattening the resultant, and annealing the flattened resultant before a gate oxide film is formed. The annealing diffuses out any contaminant existing in an area near and/or contacting the trench on a surface between a semiconductor substrate and a pad oxide film. Therefore, it is possible to prevent the portion of the gate oxide film which is near the trench from becoming thinner than other portions. Accordingly, it is possible to prevent the characteristic of the gate oxide film from deteriorating. In particular, it is possible to prevent a break down voltage from being lowered.Type: ApplicationFiled: May 21, 1999Publication date: August 15, 2002Inventors: SOO-JIN HONG, MOON-HAN PARK
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Publication number: 20020004282Abstract: A method of forming a trench isolation structure prevents a nitride liner from being over-etched, i.e., prevents the so-called dent phenomenon from occurring. An etching mask pattern is formed on a semiconductor substrate. A trench is formed in the substrate by using the etching mask pattern as an etching mask. A nitride liner, serving as an oxidation barrier layer, is formed at the sides and bottom of the trench, and is then annealed in a furnace to density the same. In a subsequent etching process, such as that used to remove the etching mask pattern, the densified nitride liner resists being etched. Accordingly, a trench isolation structure having a good profile is produced.Type: ApplicationFiled: May 3, 2001Publication date: January 10, 2002Inventor: Soo-Jin Hong
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Patent number: 6251746Abstract: Methods of forming trench isolation regions include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a trench in the semiconductor substrate, using the trench masking layer as etching mask. A trench nitride layer comprising a second material different from the first material is then formed on a sidewall of the trench and on a sidewall of the trench masking layer. The trench is then filled with a trench insulating material (e.g., USG). The trench masking layer is then removed by selectively etching the trench masking layer with an etchant that selectively etches the first material at a higher rate than the second material. This step of removing the trench masking layer results in exposure of a protruding portion of the trench nitride layer but does not cause the trench nitride layer to become recessed. The trench insulating material and the trench nitride layer are then etched back to define the trench isolation region.Type: GrantFiled: October 8, 1999Date of Patent: June 26, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Jin Hong, Yung-Seob Yu, Bon-Young Koo, Byung-Ki Kim, Seung-Mok Shin
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Patent number: 6121110Abstract: A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.Type: GrantFiled: July 29, 1998Date of Patent: September 19, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-jin Hong, Yu-gyun Shin, Han-sin Lee, Hyun-cheol Choe
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Patent number: 5677232Abstract: An isolation region is formed on a substrate by forming spaced apart mesas on the substrate. A first insulation region is then formed on the substrate and second insulation regions are formed on the mesas, the first insulation region being disposed between and spaced apart from a respective one of the mesas, a respective one of the second insulation regions capping a respective one of the mesas. Preferably, the first and second insulation regions are formed by forming sidewall spacers adjacent sidewall portions of the mesas and oxidizing portions of the mesas opposite the substrate and a portion of the substrate disposed between the sidewall spacers. Spaced apart trenches are formed in the substrate on opposite sides of the first insulation region, a respective one of the trenches being disposed between the first insulation region and a respective one of the mesas, preferably by removing the sidewall spacers and underlying portions of the substrate.Type: GrantFiled: November 22, 1996Date of Patent: October 14, 1997Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-eui Kim, Soo-jin Hong