Patents by Inventor Soo-Won Lee

Soo-Won Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240404930
    Abstract: The present disclosure provides a package structure and a related manufacturing method thereof, wherein a heat dissipation structure surrounding a chip is arranged, and an electrical connection structure is arranged on the outer side of the heat dissipation structure, so that other laminated package components can be electrically connected through a second electrical connection surface of the electrical connection structure to achieve lamination; the heat dissipation structure, the molding layer and the electrical connection structure are fastened through molding the electrical connection structure and the heat dissipation structure by the molding layer, and the molding layer and the electrical connection structure are prevented from warpage by the heat dissipation structure; finally, the package structure has the functions of heat dissipation, lamination and warpage prevention.
    Type: Application
    Filed: May 30, 2024
    Publication date: December 5, 2024
    Applicant: STATS CHIPPAC SEMICONDUCTOR (JIANGYIN) CO., LTD.
    Inventors: Jiade Liao, Jian Xu, Soo Won Lee
  • Publication number: 20240379701
    Abstract: A sensor package structure includes: a substrate; a sensor chip, displayed on the substrate and electrically connected to the substrate, where a light-receiving region is displayed on a surface, facing away from the substrate, of the sensor chip; a first package body, covering the substrate and having a chamber therein, where the light-receiving region of the sensor chip is exposed in the first chamber, and the first package body has a first opening, the first opening being in communication with the first chamber and corresponding to the light-receiving region of the sensor chip; a transparent cover plate, displayed within the first opening, where the transparent cover plate includes a first surface facing towards the first chamber and a second surface facing away from the first surface; and a second package body, displayed on the first package body.
    Type: Application
    Filed: April 10, 2024
    Publication date: November 14, 2024
    Applicant: STATS CHIPPAC SEMICONDUCTOR (JIANGYIN) CO., LTD.
    Inventors: Jeonghan KIM, Soo Won LEE, Jian XU, Hyoungill MIN, Chuanming TANG
  • Publication number: 20240363515
    Abstract: A semiconductor package structure and a forming method therefor are disclosed. The package structure includes: an encapsulant including a first and a second surfaces that are opposite and peripheral side surfaces, wherein the first surface is provided with protruding connection terminals, and junction between the first surface and the peripheral side surfaces are provided with four top corners; a substrate including a flip-chip area, wherein the flip-chip area is provided with four corner areas corresponding to four top corners of the encapsulant; trenches positioned in the substrate in the corner areas or around the corner areas or in the four corner areas and around the four corner areas at the same time; a high-modulus first underfill layer filling four trenches and spaces between the four trenches and the first surface of the encapsulant; and a low-modulus second underfill layer filling a remaining space between the encapsulant and the substrate.
    Type: Application
    Filed: April 26, 2024
    Publication date: October 31, 2024
    Applicant: STATS CHIPPAC SEMICONDUCTOR (JIANGYIN) CO., LTD.
    Inventors: Jeonghan Kim, Soo Won Lee, Jian Xu, Hyoungill Min, Ruifeng Jiang
  • Publication number: 20240363601
    Abstract: The present disclosure discloses a chip package structure and a preparation method thereof. The chip package structure includes: a metal wiring layer; a first chip, wherein a front surface of the first chip is flip-chipped on a first surface of the metal wiring layer; a first molding layer coating the first chip; a second chip, wherein a front surface of the second chip is flip-chipped on a second surface of the metal wiring layer; a first metal pillar formed on the second surface of the metal wiring layer; a second molding layer coating the second chip and the first metal pillar; and a second metal pillar formed on one side that is of the second molding layer and that is far away from the metal wiring layer, wherein the second metal pillar is at least partially connected to the corresponding first metal pillar.
    Type: Application
    Filed: April 26, 2024
    Publication date: October 31, 2024
    Applicant: STATS CHIPPAC SEMICONDUCTOR (JIANGYIN) CO., LTD.
    Inventors: Zelong Yu, Huanhuan Yuan, Jian Xu, Soo Won Lee
  • Patent number: 10394864
    Abstract: A method and a server for extracting a topic and evaluating suitability of the extracted topic are disclosed. The topic extraction server includes a text preprocessing unit configured to extract noun from a document group and remove stopword from the extracted noun, a keyword extraction unit configured to calculate a weight of a noun and extracting a keyword representing the document group, a seed selection unit configured to calculate a weight of the extracted keyword and select a seed, an initial clustering unit configured to generate one cluster including the selected seed and a keyword shown by several times in a sentence including the selected seed, and a cluster combination unit configured to extract a topic group.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: August 27, 2019
    Assignee: FOUNDATION OF SOONGSIL UNIVERSITY INDUSTRY COOPERATION
    Inventors: Soo Won Lee, Joon Ho Noh
  • Patent number: 10185996
    Abstract: Provided are a method and a system for predicting stock fluctuation prediction. A system for predicting stock fluctuation according to an embodiment of the present invention includes: a data collector and a preprocessor collecting news and KOSPI data and extracting words from the collected news through stopword removal and morphologic analysis, a sentiment dictionary constructor selecting sentiment words and calculating sentiment values of the sentiment words to construct a sentiment dictionary of a stock domain required for stock prediction, and a stock fluctuation prediction model constructor predicting fluctuation of a closing price of a next day to a closing price of a current day by combining a prediction model using the constructed sentiment dictionary and an ARIMA prediction model using the KOSPI data.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: January 22, 2019
    Assignee: FOUNDATION OF SOONGSIL UNIVERSITY INDUSTRY COOPERATION
    Inventors: Soo Won Lee, Jang Yun Um
  • Patent number: 10109587
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: October 23, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
  • Patent number: 9799621
    Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: October 24, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Soo Won Lee, Kyu Won Lee, Eun Jin Jeong
  • Publication number: 20170060997
    Abstract: A method and a server for extracting a topic and evaluating suitability of the extracted topic are disclosed. The topic extraction server includes a text preprocessing unit configured to extract noun from a document group and remove stopword from the extracted noun, a keyword extraction unit configured to calculate a weight of a noun and extracting a keyword representing the document group, a seed selection unit configured to calculate a weight of the extracted keyword and select a seed, an initial clustering unit configured to generate one cluster including the selected seed and a keyword shown by several times in a sentence including the selected seed, and a cluster combination unit configured to extract a topic group.
    Type: Application
    Filed: July 29, 2014
    Publication date: March 2, 2017
    Inventors: Soo Won LEE, Joon Ho NOH
  • Publication number: 20170032270
    Abstract: A method of predicting personality traits using a personal life log and an apparatus for performing the same are disclosed. The method of predicting personality traits comprises collecting personal life log in a social network, generating a user behavior matrix by defining an object about user's behavior through analysis of the collected personal life log in a triple structure and extracting a user behavior parameter through the generated user behavior matrix, obtaining interaction between a user and a friend by analyzing the personal life log and obtaining a friend relation characteristic parameter by using the obtained interaction, obtaining a moving path characteristic parameter by using location information made in a feed by the user through analysis of the personal life log, and predicting personality traits by applying the user behavior parameter, the friend relation characteristic parameter and the moving path characteristic parameter to four learned personality traits models.
    Type: Application
    Filed: May 29, 2014
    Publication date: February 2, 2017
    Inventors: Soo-Won LEE, Jong-Bum BAIK
  • Publication number: 20170018033
    Abstract: Provided are a method and a system for predicting stock fluctuation prediction. A system for predicting stock fluctuation according to an embodiment of the present invention includes: a data collector and a preprocessor collecting news and KOSPI data and extracting words from the collected news through stopword removal and morphologic analysis, a sentiment dictionary constructor selecting sentiment words and calculating sentiment values of the sentiment words to construct a sentiment dictionary of a stock domain required for stock prediction, and a stock fluctuation prediction model constructor predicting fluctuation of a closing price of a next day to a closing price of a current day by combining a prediction model using the constructed sentiment dictionary and an ARIMA prediction model using the KOSPI data.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 19, 2017
    Inventors: Soo Won LEE, Jang Yun UM
  • Patent number: 9412624
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: August 9, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
  • Patent number: 9384189
    Abstract: An apparatus and a method for predicting the pleasantness-unpleasantness index of words are disclosed. The disclosed apparatus includes: a computing unit configured to compute an emotion correlation between a word and one or more comparison word, compute emotion correlations between multiple reference words included in a reference word set and the one or more comparison word, compute multiple first absolute emotion similarity values between the word and the multiple reference words, and compute at least one second absolute emotion similarity value between a reference word and another reference word for all of the reference words included in the reference word set; and a prediction unit configured to predict the pleasantness-unpleasantness index of the word by using the multiple number of first absolute emotion similarity values, the at least one second absolute emotion similarity value, and a preset pleasantness-unpleasantness index of the multiple number of reference words.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: July 5, 2016
    Assignee: Foundation of Soongsil University—Industry Corporation
    Inventors: Soo Won Lee, Kang Bok Lee
  • Publication number: 20160062989
    Abstract: An apparatus and a method for predicting the pleasantness-unpleasantness index of words are disclosed. The disclosed apparatus includes: a computing unit configured to compute an emotion correlation between a word and one or more comparison word, compute emotion correlations between multiple reference words included in a reference word set and the one or more comparison word, compute multiple first absolute emotion similarity values between the word and the multiple reference words, and compute at least one second absolute emotion similarity value between a reference word and another reference word for all of the reference words included in the reference word set; and a prediction unit configured to predict the pleasantness-unpleasantness index of the word by using the multiple number of first absolute emotion similarity values, the at least one second absolute emotion similarity value, and a preset pleasantness-unpleasantness index of the multiple number of reference words.
    Type: Application
    Filed: October 21, 2014
    Publication date: March 3, 2016
    Applicant: Foundation of Soongsil Univesity-Industry Cooperation
    Inventors: Soo Won Lee, Kang Bok Lee
  • Patent number: 8956429
    Abstract: Disclosed are a cutting wheel composition, and a cutting wheel using the cutting wheel composition. The disclosed composition includes 50 to 85 wt % of abrasive particles, 10 to 25 wt % of binder resin, and balance filler, wherein the binder resin includes a phenolic resin as a first binder resin; and at least one of a (bis)maleimide resin and a cyanate ester resin as a second binder resin. The composition includes at least one of the (bis)maleimide resin and the cyanate ester resin, as well the phenolic resin, as the binder resin, and thereby makes it possible to fabricate a cutting wheel having improved life characteristics through the improvement of heat-resistance and scratch-resistance.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: February 17, 2015
    Assignee: 3M Innovative Properties Company
    Inventors: Doo-Hyun Lee, Baek-Nam Noh, Soo-Won Lee
  • Publication number: 20140327135
    Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.
    Type: Application
    Filed: July 17, 2014
    Publication date: November 6, 2014
    Inventors: Soo Won Lee, Kyu Won Lee, Eun Jin Jeong
  • Patent number: 8709932
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a contact pad; forming a first resist layer, having a first resist opening, over the carrier and the contact pad, the first resist opening partially exposing the first contact pad; forming a second resist layer, having a second resist opening over the first resist opening, the second resist opening partially exposing the first resist layer; mounting an integrated circuit over the carrier; and forming an internal interconnect between the integrated circuit and the carrier, the internal interconnect filling the second resist opening with no space between the second resist layer in the second resist opening.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: April 29, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Soo Won Lee, JiHoon Oh, Sung Jun Yoon
  • Publication number: 20130249076
    Abstract: A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the first conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Soo Won Lee, Kyu Won Lee, Eun Jin Jeong
  • Publication number: 20120149289
    Abstract: Disclosed are a cutting wheel composition, and a cutting wheel using the cutting wheel composition. The disclosed composition includes 50 to 85 wt % of abrasive particles, 10 to 25 wt % of binder resin, and balance filler, wherein the binder resin includes a phenolic resin as a first binder resin; and at least one of a (bis)maleimide resin and a cyanate ester resin as a second binder resin. The composition includes at least one of the (bis)maleimide resin and the cyanate ester resin, as well the phenolic resin, as the binder resin, and thereby makes it possible to fabricate a cutting wheel having improved life characteristics through the improvement of heat-resistance and scratch-resistance.
    Type: Application
    Filed: August 25, 2010
    Publication date: June 14, 2012
    Inventors: Doo-Hyun Lee, Baek-Nam Noh, Soo-Won Lee
  • Publication number: 20120146230
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a contact pad; forming a first resist layer, having a first resist opening, over the carrier and the contact pad, the first resist opening partially exposing the first contact pad; forming a second resist layer, having a second resist opening over the first resist opening, the second resist opening partially exposing the first resist layer; mounting an integrated circuit over the carrier; and forming an internal interconnect between the integrated circuit and the carrier, the internal interconnect filling the second resist opening with no space between the second resist layer in the second resist opening.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Inventors: Soo Won Lee, JiHoon Oh, Sung Jun Yoon