Abstract: A memory device including a memory cell array having multiple memory cells, multiple page buffers connected to the memory cells, and an enable control circuit configured to divide the page buffers into P groups, sequentially enable L groups among the P groups during an entry interval of an operation mode, and adjust a length of the entry interval of the operation mode based on a value of L, wherein P is a natural number greater than or equal to 2, and L is a natural number greater than or equal to 1 and less than or equal to P.

Abstract: A memory device includes a memory block having multiple string groups, and a controller configured to repeat one or more erase loops, each erase loop including a pulse application interval and a verification interval, configured to determine the multiple string groups as one of pass and fail string groups in a verification interval of a previous erase loop, and configured to apply a first voltage to a drain selection line corresponding to the fail string group from start timing to first timing, apply the first voltage to a drain selection line corresponding to the pass string group from the start timing to second timing earlier than the first timing, and apply a second voltage to the drain selection line from the second timing to the first timing in a pulse application interval of a subsequent erase loop subsequent to the previous erase loop.

Abstract: A memory device includes: a plurality of page buffers connected a plurality of bit lines and configured to selectively precharge the bit lines, and a control circuit configured to: perform a first verify operation by applying a precharge voltage to a first bit line among the bit lines according to program data and by applying a first verify voltage to a selected word line, perform a second verify operation, after the first verify operation, by applying the precharge voltage to a second bit line not overlapping the first bit line and by applying a second verify voltage to the selected word line, and perform at least one of an operation of floating the first bit line and an operation of applying the precharge voltage according to a threshold voltage of a memory cell connected to the first bit line during the second verify operation.

Abstract: A memory device may include a plurality of memory cells, a peripheral circuit configured to perform a plurality of program loops on selected memory cells among the plurality of memory cells, each of the plurality of program loops including a program pulse application operation and a program verify operation, and control logic configured to control the peripheral circuit to suspend an nth program loop (n is a natural number equal to or greater than 1) among the plurality of program loops in response to a suspend command received during the nth program loop, and to resume the nth program loop with a negative verify operation in response to a resume command. The negative verify operation applies a negative voltage having a voltage less than a state voltage at the time of application of the resume command.

Abstract: A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node, based on a cell current amount of the bit line, by performing an evaluation operation. The page buffer also includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verify data, based on the potential level of the sensing node.

Abstract: A memory device comprising: a memory cell array, and a controller configured to connect, in a first interval equal to or longer than a bit line setup interval, each of first and second bit lines, which are connected to cells respectively having first and second program states, to a node of a first permission voltage, connect, in the first interval, a third bit line, which is connected to a cell having a program prohibition state, to a node of a prohibition voltage, maintain, in a second interval that is equal to or shorter than a program pulse application interval, the respective connections of the first bit line and the third bit line, and disconnect, in the second interval, the second bit line from the node of the first permission voltage to apply the second bit line with a second permission voltage.

Abstract: A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node, based on a cell current amount of the bit line, by performing an evaluation operation. The page buffer also includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verify data, based on the potential level of the sensing node.

Abstract: The present technology provides a method of operating a semiconductor memory device detecting a threshold voltage distribution for memory cells included in a page selected from among a plurality of memory cells. The method of operating the semiconductor memory device includes selecting a target state in which the threshold voltage distribution is to be detected, determining a plurality of read voltages for dividing a voltage range in which a threshold voltage of the selected target state is distributed, and performing a plurality of sensing operations using the plurality of read voltages on the selected page. Masking to the target state is applied in each of the plurality of sensing operations.

Abstract: A memory device includes: a plurality of page buffers connected a plurality of bit lines and configured to selectively precharge the bit lines, and a control circuit configured to: perform a first verify operation by applying a precharge voltage to a first bit line among the bit lines according to program data and by applying a first verify voltage to a selected word line, perform a second verify operation, after the first verify operation, by applying the precharge voltage to a second bit line not overlapping the first bit line and by applying a second verify voltage to the selected word line, and perform at least one of an operation of floating the first bit line and an operation of applying the precharge voltage according to a threshold voltage of a memory cell connected to the first bit line during the second verify operation.

Abstract: A page buffer circuit may include: a data transfer circuit configured to transfer data, transferred to a first sensing node through a bit line, to a second sensing node during a data sensing operation; a first latch circuit configured to sense the data transferred to the first sensing node, and store the sensed data; and a second latch circuit configured to sense the data transferred to the second sensing node, and store the sensed data.

Abstract: A memory device may include a plurality of memory cells, a peripheral circuit configured to perform a plurality of program loops on selected memory cells among the plurality of memory cells, each of the plurality of program loops including a program pulse application operation and a program verify operation, and control logic configured to control the peripheral circuit to suspend an nth program loop (n is a natural number equal to or greater than 1) among the plurality of program loops in response to a suspend command received during the nth program loop, and to resume the nth program loop with a negative verify operation in response to a resume command. The negative verify operation applies a negative voltage having a voltage less than a state voltage at the time of application of the resume command.

Abstract: A memory device includes a cell wafer having a first pad on one surface thereof; and a peripheral wafer bonded to the one surface of the cell wafer, and having a second pad coupled to the first pad. The cell wafer includes a memory cell array; first and second bit lines coupled to the memory cell array; and a bit line selection circuit configured to couple one of the first and second bit lines to the first pad. The peripheral wafer includes a page buffer low-voltage circuit including a first page buffer low-voltage unit corresponding to the first bit line and a second page buffer low-voltage unit corresponding to the second bit line; and a page buffer high-voltage circuit configured to couple one of the first and second page buffer low-voltage units to the second pad.

Abstract: Provided herein may be a memory device having a page buffer. The memory device may include a memory cell configured to store data, and a page buffer coupled to the memory cell through a bit line and configured to store data to be used in a program operation and to precharge the bit line to a first precharge voltage or a second precharge voltage lower than the first precharge voltage depending on the data during a program verify operation performed in the program operation.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory cells, and a peripheral circuit configured to apply a plurality of operating voltages to a plurality of word lines of the memory block during a program operation, wherein, during a verify operation included in the program operation, the peripheral circuit may be configured to allow a selected word line, among the plurality of word lines, to float, and may decrease a potential of the selected word line to a pre-level by decreasing potentials of adjacent word lines to the selected word line.

Abstract: The present technology includes a memory device. The memory device includes memory cells, page buffers configured to store sensed data obtained from the memory cells, a current sensing circuit configured to compare a sensed voltage generated according to the sensed data and a reference voltage generated according to an allowable fail bit code, and output a pass signal or a fail signal according to a comparison result, and a fail bit manager configured to increase an allowable number of fail bits included in the allowable fail bit code until the pass signal is output from the current sensing circuit, change the allowable fail bit code according to the allowable number of fail bits, and provide the allowable fail bit code to the current sensing circuit.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to program the plurality of memory cells to a plurality of program states, and a control logic configured to control the peripheral circuit so that program operations corresponding to the plurality of program states are performed, wherein the control logic controls the peripheral circuit so that, during a program operation for a target program state, among the plurality of program states, memory cells to be programmed to an immediately higher program state than the target program state are programmed to the target program state.

Abstract: The present technology relates to an electronic device. A memory device capable of reducing a time consumed in a program operation includes a memory cell array, a page buffer group connected to the memory cell array through a plurality of bit lines and a voltage generator configured to generate voltages to apply to each of a plurality of page buffers included in the page buffer group. Each of the plurality of page buffers includes a precharge circuit that controls potential levels of the plurality of bit lines to be maintained at precharge levels.

Abstract: The present technology provides a method of operating a semiconductor memory device detecting a threshold voltage distribution for memory cells included in a page selected from among a plurality of memory cells. The method of operating the semiconductor memory device includes selecting a target state in which the threshold voltage distribution is to be detected, determining a plurality of read voltages for dividing a voltage range in which a threshold voltage of the selected target state is distributed, and performing a plurality of sensing operations using the plurality of read voltages on the selected page. Masking to the target state is applied in each of the plurality of sensing operations.

Abstract: A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node, based on a cell current amount of the bit line, by performing an evaluation operation. The page buffer also includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verify data, based on the potential level of the sensing node.

Abstract: The present technology includes a memory device. The memory device includes memory cells, page buffers configured to store sensed data obtained from the memory cells, a current sensing circuit configured to compare a sensed voltage generated according to the sensed data and a reference voltage generated according to an allowable fail bit code, and output a pass signal or a fail signal according to a comparison result, and a fail bit manager configured to increase an allowable number of fail bits included in the allowable fail bit code until the pass signal is output from the current sensing circuit, change the allowable fail bit code according to the allowable number of fail bits, and provide the allowable fail bit code to the current sensing circuit.