Abstract: The present disclosure relates to a memory device. The memory device includes first memory cell strings, second memory cell strings, a peripheral circuit, and a control logic. The peripheral circuit is connected to first drain select transistors of each of the first memory cell strings through first bit lines, and is connected to second drain select transistors of each of the second memory cell strings through second bit lines. The control logic controls the peripheral circuit to increase a potential of a program inhibit bit line among the first bit lines to a first voltage, and float the program inhibit bit line and increase a potential of the second bit line to a second voltage after the potential of the program inhibit bit line increases to the first voltage.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to program the plurality of memory cells to a plurality of program states, and a control logic configured to control the peripheral circuit so that program operations corresponding to the plurality of program states are performed, wherein the control logic controls the peripheral circuit so that, during a program operation for a target program state, among the plurality of program states, memory cells to be programmed to an immediately higher program state than the target program state are programmed to the target program state.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation.

Abstract: There are provided a memory device and an operating method thereof. The memory device includes memory cells connected between a bit line and a source line, a voltage generator for generating program voltages and verify voltages which are to be applied to a selected word line connected to a selected memory cell, a page buffer for storing data respectively sensed in verify operations using the verify voltages, and for transferring a program allow voltage, a program inhibit voltage or a program control voltage to the bit line by sequentially using the data, and a logic circuit for generating page buffer control signals for controlling the page buffer.

Abstract: The present disclosure relates to a memory device. The memory device includes first memory cell strings, second memory cell strings, a peripheral circuit, and a control logic. The peripheral circuit is connected to first drain select transistors of each of the first memory cell strings through first bit lines, and is connected to second drain select transistors of each of the second memory cell strings through second bit lines. The control logic controls the peripheral circuit to increase a potential of a program inhibit bit line among the first bit lines to a first voltage, and float the program inhibit bit line and increase a potential of the second bit line to a second voltage after the potential of the program inhibit bit line increases to the first voltage.