Patents by Inventor Soon-Moon Jung

Soon-Moon Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200017705
    Abstract: Disclosed is a coating material for a coating layer of an injection mold, the coating material including 100 parts by weight of a resin composition and about 30 to 40 parts by weight of a curing agent. The resin composition includes an amount of about 40 to 50 wt % of a first acrylic resin, an amount of about 5 to 15 wt % of a second acrylic resin having a weight average molecular weight less than a weight average molecular weight of the first acrylic resin, an amount of about 10 to 15 wt % of a carbon component, an amount of about 0.5 to 2 wt % of a matting agent, an amount of about 0.1 to 0.3 wt % of a catalyst and an amount of about 20 to 35 wt % of a solvent, all the wt % are based on the total weight of the resin composition.
    Type: Application
    Filed: November 5, 2018
    Publication date: January 16, 2020
    Inventors: Kyeong Hoon Jang, In Soo Han, Dae Sik Kim, Jae Hyun An, Seul Yi, Ik Jin Jung, Ju Seong Park, Soon Joon Jung, Seung Sik Han, Jae Beom Ahn, Yong Chul Lee, Kie Moon Sung, Soon Gi Kim, Hak Soon Choi
  • Patent number: 8399308
    Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: March 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Chul Jang, Won-Seok Cho, Jae-Hoon Jang, Soon-Moon Jung, Yang-Soo Son, Min-Sung Song
  • Patent number: 8343812
    Abstract: On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sung Song, Soon-Moon Jung, Han-Soo Kim, Young-Seop Rah, Won-Seok Cho, Yang-Soo Son, Jong-Hyuk Kim, Young-Chul Jang
  • Patent number: 8324045
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Beom Park, Soon-Moon Jung, Ki-Nam Kim
  • Patent number: 8258563
    Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: September 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Chul Jang, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Patent number: 8258517
    Abstract: One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: September 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-In Yun, Soon-Moon Jung, Han-Soo Kim, Hoo-Sung Cho, Jun-Beom Park, Jae-Hun Jeong
  • Patent number: 8248853
    Abstract: In a method of programming a non-volatile memory device, a first voltage is applied to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; a second voltage is applied to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor; wherein the neighboring transistor is positioned between the selected memory cell transistor and one of a ground select transistor and a string select transistor, and the first voltage is
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: August 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Duk Lee, Soon Moon Jung, Jung Dal Choi
  • Patent number: 8227306
    Abstract: In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jonghyuk Kim, Han-Soo Kim, YoungSeop Rah, Min-sung Song, Jang Young Chul, Soon-Moon Jung, Wonseok Cho
  • Patent number: 8227919
    Abstract: An interconnection structure and an electronic device employing the same are provided. The interconnection structure for an integrated structure includes first and second contact plugs disposed on a substrate, and a connection pattern interposed between sidewalls of the first and second contact plugs and configured to electrically connect the first and second contact plugs.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Byung Park, Soon-Moon Jung, Hoon Lim
  • Patent number: 8183634
    Abstract: A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Beom Park, Soon-Moon Jung, Han-Soo Kim, Jae-Hoon Jang, Jae-Hun Jeong, Jong-In Yun, Mi-So Hwang
  • Patent number: 8168530
    Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: May 1, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Publication number: 20120009767
    Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
    Type: Application
    Filed: September 19, 2011
    Publication date: January 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Chul JANG, Won-Seok Cho, Jae-Hoon Jang, Soon-Moon Jung, Yang-Soo Son, Min-Sung Song
  • Patent number: 8084306
    Abstract: A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: December 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hun Jeong, Hoon Lim, Soon-Moon Jung, Hoo-Sung Cho
  • Publication number: 20110300683
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.
    Type: Application
    Filed: August 15, 2011
    Publication date: December 8, 2011
    Inventors: Jun-Beom Park, Soon-Moon Jung, Ki-Nam Kim
  • Publication number: 20110287590
    Abstract: On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.
    Type: Application
    Filed: August 5, 2011
    Publication date: November 24, 2011
    Inventors: Min-Sung Song, Soon-Moon Jung, Han-Soo Kim, Young-Seop Rah, Won-Seok Cho, Yang-Soo Son, Jong-Hyuk KIm, Young-Chul Jang
  • Patent number: 8054688
    Abstract: Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The plurality of non-volatile memory cell transistors are grouped into two or more memory cell blocks, such that a first voltage is applied to the first semiconductor substrate including a first memory cell block to be erased, and either (1) a second voltage less than the first voltage and greater than 0V is applied to the second semiconductor substrate not including the first memory cell block, or (2) the second semiconductor substrate not including the first memory cell block is allowed to electrically float.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hun Jeong, Soon-moon Jung, Han-soo Kim, Jae-hoon Jang
  • Publication number: 20110266623
    Abstract: A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.
    Type: Application
    Filed: July 18, 2011
    Publication date: November 3, 2011
    Inventors: Gong-Heum Han, Hyou-Youn Nam, Bo-Tak Lim, Han-Byung Park, Soon-Moon Jung, Hoon Lim
  • Patent number: 8048727
    Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hoon Jang, Soon-Moon Jung, Young-Seop Rah, Han-Byung Park
  • Patent number: 8040733
    Abstract: A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to commonly receive a bias voltage. The non-volatile memory device also includes dummy cell transistors connected to the first and second strings, and first and second dummy word lines configured to receive different bias voltages.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hun Jeong, Soon-moon Jung, Han-soo Kim, Jae-hoon Jang
  • Patent number: 8034668
    Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: October 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Chul Jang, Won-Seok Cho, Jae-Hoon Jang, Soon-Moon Jung, Yang-Soo Son, Min-Sung Song