Abstract: A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

Abstract: Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

Abstract: Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

Abstract: Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

Abstract: A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.

Abstract: A transistor and a method of fabricating the same: The transistor includes an isolation layer disposed in a semiconductor substrate to define an active region. A pair of source/drain regions is disposed in the active region, spaced apart from each other. A channel region is interposed between the pair of the source/drain regions. The active region has a mesa disposed across the channel region. The mesa extends to the source/drain regions. A gate electrode is disposed to cross the active region along the direction across the mesa.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extends onto the device isolation layer. The epitaxial layer is spaced apart from the sidewall of the vertically protruding portion of the device isolation layer. A gate pattern is provided on the epitaxial layer and source/drain regions are provided in the epitaxial layer at opposite sides of the gate pattern.

Abstract: SRAM cells and devices are provided. The SRAM cells may share connections with neighboring cells, including ground, power supply voltage and/or bit line connections. SRAM cells and devices are also provided that include first and second active regions disposed at a semiconductor substrate. Parallel first and second gate electrodes cross over the first and second active regions. One end of the first active region adjacent to the first gate electrode is electrically connected to the second active region adjacent to the first gate electrode through a first node line parallel to the first gate electrode, and the other end of the first active region adjacent to the second gate electrode is electrically connected to the second active region adjacent to the second gate electrode through a second node line parallel to the second gate electrode.

Abstract: A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.

Abstract: An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode.

Abstract: An interconnection structure is provided by foiling a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode.

Abstract: Semiconductor devices that include a semiconductor substrate and a gate line are provided. The gate line is on the semiconductor substrate and includes a gate insulation pattern and a gate electrode which are stacked on the substrate in the order named. A spacer is on a sidewall of the gate line. A conductive line pattern is on the gate line. The conductive line pattern is parallel with the gate line and is electrically connected to the gate electrode.

Abstract: Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings.

Abstract: An interconnection structure is provided by foiling a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode.

Abstract: SRAM cells and devices are provided. The SRAM cells may share connections with neighboring cells, including ground, power supply voltage and/or bit line connections. SRAM cells and devices are also provided that include first and second active regions disposed at a semiconductor substrate. Parallel first and second gate electrodes cross over the first and second active regions. One end of the first active region adjacent to the first gate electrode is electrically connected to the second active region adjacent to the first gate electrode through a first node line parallel to the first gate electrode, and the other end of the first active region adjacent to the second gate electrode is electrically connected to the second active region adjacent to the second gate electrode through a second node line parallel to the second gate electrode.

Abstract: A method of forming a contact structure in a semiconductor device is provided. In this method, a semiconductor layer, an ohmic metal layer, and a barrier metal layer are formed on the surface of a semiconductor substrate on which a metal contact hole has been formed. A compound material layer having a uniform thickness is formed on the bottom, sidewalls and lower corners of the contact hole by thermally reacting the semiconductor layer with the ohmic metal layer. Accordingly, when the contact hole exposes an impurity layer and portions of an isolation layer adjacent to the impurity layer, the junction leakage current characteristics of the impurity layer and a contact resistance are improved.

Abstract: A method of forming contact holes of a semiconductor device wherein process yield is improved and manufacturing processes can be simplified. First, a plurality of gate electrodes provided with a plurality of spacers are formed on an active region of a semiconductor substrate that is separated into the active region and a field region by a field oxide layer. Then, the outermost spacers are removed from the plurality of spacers, to ensure a space for a first contact hole on the semiconductor substrate. Next, an etch stopping layer and an interlayer dielectric are subsequently formed on the semiconductor substrate.

Abstract: A semiconductor memory device is disclosed. The device is comprised of a plurality of word lines; a plurality of bit lines arranged in perpendicular to the word lines. In addition, a plurality of supply voltage lines extend in the same direction as the bit lines. Also, a plurality of first ground voltage lines are arranged in the same direction as the bit lines. Further, a plurality of second ground voltage lines are arranged in the same direction as the word lines. A plurality of memory cells are each connected between one of the word lines and one of the bit lines. Here, the ground voltage lines are arranged in a matrix shape to reduce the resistance of the ground voltage line and secure the margin between the supply voltage level and the ground voltage level of the data latched by the memory cells to thereby prevent an operational failure of the device.

Abstract: A method of forming contact holes of a semiconductor device wherein process yield is improved and manufacturing processes can be simplified. First, a plurality of gate electrodes provided with a plurality of spacers are formed on an active region of a semiconductor substrate that is separated into the active region and a field region by a field oxide layer. Then, the outermost spacers are removed from the plurality of spacers, to ensure a space for a first contact hole on the semiconductor substrate. Next, an etch stopping layer and an interlayer dielectric are subsequently formed on the semiconductor substrate.

Abstract: A SRAM cell includes a single line used as both a word line and a power supply voltage line, a first and a second load element, a first and a second NMOS driver transistor, and a first and a second PMOS access transistor. Each of the two load elements is connected between the line and one of two storage nodes. The first load element is connected between the single line and a first storage node. The second load element is connected between the single line and a second storage node. The first NMOS driver transistor is connected between the first storage node and ground. The second driver transistor is connected between the second storage node and ground. The first access transistor is connected between the first storage node and a bit line and the second access transistor is connected between the second storage node and a complementary bit line. The first and second access transistors have gates commonly connected to the single line.