Patents by Inventor Souichi Yoshida
Souichi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9614106Abstract: In an IGBT portion, a first gate electrode is provided in a first trench via a first gate insulating film. A thickness of a first gate insulating film lower portion is thicker than a thickness of a first gate insulating film upper portion, whereby a width of a mesa portion between adjacent first trenches is narrower at a portion of a collector side than at an emitter side. In a diode portion, a second gate electrode is provided inside a second trench via second gate insulating film. A width of the second trench is uniform along a depth direction or narrows from the emitter side toward the collector side. Widths of the second trench are narrower than a sum of a width of the first trench lower portion and the thickness of the first gate insulating film lower portion of both side walls of the first trench lower portion.Type: GrantFiled: December 4, 2015Date of Patent: April 4, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventor: Souichi Yoshida
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Publication number: 20170047322Abstract: A semiconductor device, including a semiconductor substrate, a plurality of trenches formed on a front surface of the semiconductor substrate, a plurality of gate electrodes formed in the trenches, a base region and an anode region formed between adjacent trenches respectively in first and second element regions of the semiconductor substrate, a plurality of emitter regions and contact regions selectively formed in the base region, an interlayer insulating film covering the gate electrodes, first and second contact holes penetrating the interlayer insulating film, a plurality of contact plugs embedded in the first contact holes, a first electrode contacting the contact plugs and contacting the anode region via the second contact hole, a collector region and a cathode region formed on a back surface of the semiconductor substrate respectively in the first and second element regions, and a second electrode contacting the collector region and the cathode region.Type: ApplicationFiled: October 28, 2016Publication date: February 16, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Souichi YOSHIDA, Hiroshi MIYATA
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Patent number: 9536875Abstract: An IGBT is disposed in an IGBT portion, and an FWD is disposed in an FWD portion. A p-type base region and an n?-type drift region are alternately exposed in a trench longitudinal direction in a substrate front surface in a mesa portion between neighboring trenches in the IGBT portion. A p-type anode region and the n?-type drift region are alternately exposed in the trench longitudinal direction in the substrate front surface in a mesa portion in the FWD portion, and a repetitive structure is formed with a portion of the n?-type drift region sandwiched between p-type anode regions and one p-type anode region in contact with the portion as one unit region. The proportion occupied by the p-type anode region in one unit region (an anode ratio) (?) is 50% to 100%.Type: GrantFiled: October 13, 2015Date of Patent: January 3, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Masaki Tamura, Souichi Yoshida, Shinichiro Adachi
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Publication number: 20160211257Abstract: In an IGBT portion, a first gate electrode is provided in a first trench via a first gate insulating film. A thickness of a first gate insulating film lower portion is thicker than a thickness of a first gate insulating film upper portion, whereby a width of a mesa portion between adjacent first trenches is narrower at a portion of a collector side than at an emitter side. In a diode portion, a second gate electrode is provided inside a second trench via second gate insulating film. A width of the second trench is uniform along a depth direction or narrows from the emitter side toward the collector side. Widths of the second trench are narrower than a sum of a width of the first trench lower portion and the thickness of the first gate insulating film lower portion of both side walls of the first trench lower portion.Type: ApplicationFiled: December 4, 2015Publication date: July 21, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventor: Souichi YOSHIDA
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Publication number: 20160043073Abstract: An IGBT is disposed in an IGBT portion, and an FWD is disposed in an FWD portion. A p-type base region and an n?-type drift region are alternately exposed in a trench longitudinal direction in a substrate front surface in a mesa portion between neighboring trenches in the IGBT portion. A p-type anode region and the n?-type drift region are alternately exposed in the trench longitudinal direction in the substrate front surface in a mesa portion in the FWD portion, and a repetitive structure is formed with a portion of the n?-type drift region sandwiched between p-type anode regions and one p-type anode region in contact with the portion as one unit region. The proportion occupied by the p-type anode region in one unit region (an anode ratio) (?) is 50% to 100%.Type: ApplicationFiled: October 13, 2015Publication date: February 11, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Masaki TAMURA, Souichi YOSHIDA, Shinichiro ADACHI
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Patent number: 9023692Abstract: IGBT and diode are formed with optimal electrical characteristics on the same semiconductor substrate. IGBT region and FWD region are provided on the same semiconductor substrate. There are a plurality of trenches at predetermined intervals in the front surface of an n? type semiconductor substrate, and P-type channel regions at predetermined intervals in the longitudinal direction of the trench between neighboring trenches, thereby configuring a MOS gate. The p-type channel region and n? type drift region are alternately disposed in longitudinal direction of the trench in the IGBT region. The p-type channel region and a p? type spacer region are alternately disposed in the longitudinal direction of the trench in the FWD region. Pitch in longitudinal direction of the trench of p-type channel region in the IGBT region is shorter than pitch in longitudinal direction of the trench of p-type channel region in the FWD region.Type: GrantFiled: September 12, 2013Date of Patent: May 5, 2015Assignee: Fuji Electric Co., Ltd.Inventors: Souichi Yoshida, Toshihito Kamei, Seiji Noguchi
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Publication number: 20140070270Abstract: IGBT and diode are formed with optimal electrical characteristics on the same semiconductor substrate. IGBT region and FWD region are provided on the same semiconductor substrate. There are a plurality of trenches at predetermined intervals in the front surface of an n? type semiconductor substrate, and P-type channel regions at predetermined intervals in the longitudinal direction of the trench between neighboring trenches, thereby configuring a MOS gate. The p-type channel region and n? type drift region are alternately disposed in longitudinal direction of the trench in the IGBT region. The p-type channel region and a p? type spacer region are alternately disposed in the longitudinal direction of the trench in the FWD region. Pitch in longitudinal direction of the trench of p-type channel region in the IGBT region is shorter than pitch in longitudinal direction of the trench of p-type channel region in the FWD region.Type: ApplicationFiled: September 12, 2013Publication date: March 13, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Souichi YOSHIDA, Toshihito KAMEI, Seiji NOGUCHI
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Patent number: 8502345Abstract: Reverse-conducting insulated gate bipolar transistor in which IGBT region and FWD region are integrated into a single body in a semiconductor substrate with a common active region is disclosed. MOS gate structure is on a first major surface side. Rear surface side structure is in a second major surface side of the semiconductor substrate and includes a plurality of recessed parts vertical to the second major surface, which are repeated periodically along the second major surface. A plurality of protruding parts are interposed between the recessed parts. Rear surface side structure includes p type collector region on a bottom surface of the recessed part, n type first field stop region at a position deeper than the collector region, n type cathode region on the top surface of the protruding part, and n type second field stop region in the protruding part at a position deeper than the cathode region.Type: GrantFiled: January 27, 2011Date of Patent: August 6, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Michio Nemoto, Souichi Yoshida
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Publication number: 20110186965Abstract: Reverse-conducting insulated gate bipolar transistor in which IGBT region and FWD region are integrated into a single body in a semiconductor substrate with a common active region is disclosed. MOS gate structure is on a first major surface side. Rear surface side structure is in a second major surface side of the semiconductor substrate and includes a plurality of recessed parts vertical to the second major surface, which are repeated periodically along the second major surface. A plurality of protruding parts are interposed between the recessed parts. Rear surface side structure includes p type collector region on a bottom surface of the recessed part, n type first field stop region at a position deeper than the collector region, n type cathode region on the top surface of the protruding part, and n type second field stop region in the protruding part at a position deeper than the cathode region.Type: ApplicationFiled: January 27, 2011Publication date: August 4, 2011Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.Inventors: Michio NEMOTO, Souichi YOSHIDA
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Patent number: 7230058Abstract: The disclosure is directed to a partially hydrogenated ring-opened polynorbornene and a process for making the same. The ring-opened polynorbornene is low in birefringence, high in wavelength dependency about birefringence and excellent in transparency and heat resistance.Type: GrantFiled: February 27, 2006Date of Patent: June 12, 2007Assignee: JSR CorporationInventors: Nobuyuki Miyaki, Yoshikazu Miyamoto, Souichi Yoshida, Yuichi Hashiguchi
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Patent number: 7157523Abstract: The disclosure is directed to a partially hydrogenated ring-opened polynorbornene and a process for making the same. The ring-opened polynorbornene is low in birefringence, high in wavelength dependency about birefringence and excellent in transparency and heat resistance.Type: GrantFiled: November 12, 2003Date of Patent: January 2, 2007Assignee: JSR CorporationInventors: Nobuyuki Miyaki, Yoshikazu Miyamoto, Souichi Yoshida, Yuichi Hashiguchi
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Publication number: 20060189771Abstract: The invention provides a ring-opened norbornene polymer that is relatively small in birefringence, has specific wavelength dependency about birefringence and is excellent in transparency and heat resistance.Type: ApplicationFiled: February 27, 2006Publication date: August 24, 2006Applicant: JSR CorporationInventors: Nobuyuki Miyaki, Yoshikazu Miyamoto, Souichi Yoshida, Yuichi Hashiguchi
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Publication number: 20060041092Abstract: The invention provides a ring-opened polynorbornene that is relatively low in birefringence, has specific wavelength dependency about birefringence and is excellent in transparency and heat resistance.Type: ApplicationFiled: November 12, 2003Publication date: February 23, 2006Applicant: JSR CorporationInventors: Nobuyuki Miyaki, Yoshikazu Miyamoto, Souichi Yoshida, Yuichi Hashiguchi