Patents by Inventor Sourabh Dhir

Sourabh Dhir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160155745
    Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.
    Type: Application
    Filed: January 25, 2016
    Publication date: June 2, 2016
    Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
  • Patent number: 9349737
    Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: May 24, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Sourabh Dhir, Rajesh N. Gupta, Sanh D. Tang, Si-Woo Lee, Haitao Liu
  • Publication number: 20160104709
    Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 14, 2016
    Inventors: Srinivas Pulugurtha, Sourabh Dhir, Rajesh N. Gupta, Sanh D. Tang, Si-Woo Lee, Haitao Liu
  • Patent number: 9263455
    Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: February 16, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
  • Publication number: 20150243748
    Abstract: A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. An opposing sidewall of the semiconductive pillar is not adjacent the gate electrode or another gate electrode. Semiconductive device structures, methods of forming a vertical access device, and methods of forming a semiconductive structure are also described.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Inventors: Srinivas Pulugurtha, Haitao Liu, Sanh D. Tang, Wolfgang Mueller, Sourabh Dhir
  • Publication number: 20150129955
    Abstract: A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Wolfgang Mueller, Sanh D. Tang, Sourabh Dhir, Srinivas Pulugurtha
  • Publication number: 20150028406
    Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu