Patents by Inventor Sourabh Dhir
Sourabh Dhir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11868638Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.Type: GrantFiled: September 11, 2020Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Sourabh Dhir, Kang-Yong Kim
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Patent number: 11621031Abstract: In some examples, memory die may include a selection pad, which may be coupled to a power potential. The selection pad may provide a signal to a selection control circuit, which may control a selection circuit to couple a power pad to one of multiple power rails. In some examples, a power management integrated circuit may include a selection circuit to provide one power potential to a package including a memory die when a selection signal has a logic level and another power potential when the selection signal has another logic level.Type: GrantFiled: April 27, 2021Date of Patent: April 4, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Hyun Yoo Lee, Kang-Yong Kim, Sourabh Dhir, Keun Soo Song
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Publication number: 20220343963Abstract: In some examples, memory die may include a selection pad, which may be coupled to a power potential. The selection pad may provide a signal to a selection control circuit, which may control a selection circuit to couple a power pad to one of multiple power rails. In some examples, a power management integrated circuit may include a selection circuit to provide one power potential to a package including a memory die when a selection signal has a logic level and another power potential when the selection signal has another logic level.Type: ApplicationFiled: April 27, 2021Publication date: October 27, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Hyun Yoo Lee, Kang-Yong Kim, Sourabh Dhir, Keun Soo Song
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Patent number: 11462544Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.Type: GrantFiled: October 16, 2018Date of Patent: October 4, 2022Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
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Publication number: 20220066675Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.Type: ApplicationFiled: September 11, 2020Publication date: March 3, 2022Inventors: Sourabh Dhir, Kang-Yong Kim
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Patent number: 10607851Abstract: Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.Type: GrantFiled: August 25, 2017Date of Patent: March 31, 2020Assignee: Micron Technology, Inc.Inventors: Andrew L. Li, Prashant Raghu, Sanjeev Sapra, Rita J. Klein, Sanh D. Tang, Sourabh Dhir
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Publication number: 20190067028Abstract: Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.Type: ApplicationFiled: August 25, 2017Publication date: February 28, 2019Inventors: Andrew L. Li, Prashant Raghu, Sanjeev Sapra, Rita J. Klein, Sanh D. Tang, Sourabh Dhir
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Publication number: 20190051653Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.Type: ApplicationFiled: October 16, 2018Publication date: February 14, 2019Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
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Patent number: 10163908Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.Type: GrantFiled: January 25, 2016Date of Patent: December 25, 2018Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
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Patent number: 10128183Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.Type: GrantFiled: March 20, 2018Date of Patent: November 13, 2018Assignee: Micron Technology, Inc.Inventors: Sourabh Dhir, Andrew L. Li, Sanh D. Tang, Naoyoshi Kobayashi, Katsumi Koge
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Publication number: 20180323142Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.Type: ApplicationFiled: March 20, 2018Publication date: November 8, 2018Applicant: Micron Technology, Inc.Inventors: Sourabh Dhir, Andrew L. Li, Sanh D. Tang, Naoyoshi Kobayashi, Katsumi Koge
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Patent number: 9960114Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.Type: GrantFiled: May 3, 2017Date of Patent: May 1, 2018Assignee: Micron Technology, Inc.Inventors: Sourabh Dhir, Andrew L. Li, Sanh D. Tang, Naoyoshi Kobayashi, Katsumi Koge
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Patent number: 9773888Abstract: A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. An opposing sidewall of the semiconductive pillar is not adjacent the gate electrode or another gate electrode. Semiconductive device structures, methods of forming a vertical access device, and methods of forming a semiconductive structure are also described.Type: GrantFiled: February 26, 2014Date of Patent: September 26, 2017Assignee: Micron Technology, Inc.Inventors: Srinivas Pulugurtha, Haitao Liu, Sanh D. Tang, Wolfgang Mueller, Sourabh Dhir
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Patent number: 9761590Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.Type: GrantFiled: May 23, 2016Date of Patent: September 12, 2017Assignee: Micron Technology, Inc.Inventors: Srinivas Pulugurtha, Sourabh Dhir, Rajesh N. Gupta, Sanh D. Tang, Si-Woo Lee, Haitao Liu
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Patent number: 9564442Abstract: A method of forming contacts for a semiconductor device structure comprises forming contact holes extending into neighboring semiconductive pillars and into a nitride material of nitride-capped electrodes. Composite structures are formed within the contact holes and comprise oxide structures over sidewalls of the contact holes and nitride structures over the oxide structures. Conductive structures are formed over inner sidewalls of the composite structures. Additional nitride-capped electrodes are formed over the conductive structures and extend perpendicular to the nitride-capped electrodes. Pairs of nitride spacers are formed over opposing sidewalls of the additional nitride-capped electrodes and are separated from neighboring pairs of nitride spacers by apertures extending to upper surfaces of a portion of the neighboring semiconductive pillars. Portions of the oxide structures are removed to expose sidewalls of the portion of the neighboring semiconductive pillars.Type: GrantFiled: April 8, 2015Date of Patent: February 7, 2017Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Wolfgang Mueller, Sourabh Dhir, Dylan R. MacMaster
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Publication number: 20160300842Abstract: A method of forming contacts for a semiconductor device structure comprises forming contact holes extending into neighboring semiconductive pillars and into a nitride material of nitride-capped electrodes. Composite structures are formed within the contact holes and comprise oxide structures over sidewalls of the contact holes and nitride structures over the oxide structures. Conductive structures are formed over inner sidewalls of the composite structures. Additional nitride-capped electrodes are formed over the conductive structures and extend perpendicular to the nitride-capped electrodes. Pairs of nitride spacers are formed over opposing sidewalls of the additional nitride-capped electrodes and are separated from neighboring pairs of nitride spacers by apertures extending to upper surfaces of a portion of the neighboring semiconductive pillars. Portions of the oxide structures are removed to expose sidewalls of the portion of the neighboring semiconductive pillars.Type: ApplicationFiled: April 8, 2015Publication date: October 13, 2016Inventors: Sanh D. Tang, Wolfgang Mueller, Sourabh Dhir, Dylan R. MacMaster
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Patent number: 9373715Abstract: A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed.Type: GrantFiled: November 8, 2013Date of Patent: June 21, 2016Assignee: Micron Technology, Inc.Inventors: Wolfgang Mueller, Sanh D. Tang, Sourabh Dhir, Srinivas Pulugurtha
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Publication number: 20160155745Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.Type: ApplicationFiled: January 25, 2016Publication date: June 2, 2016Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
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Patent number: 9349737Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.Type: GrantFiled: October 10, 2014Date of Patent: May 24, 2016Assignee: Micron Technology, Inc.Inventors: Srinivas Pulugurtha, Sourabh Dhir, Rajesh N. Gupta, Sanh D. Tang, Si-Woo Lee, Haitao Liu
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Publication number: 20160104709Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.Type: ApplicationFiled: October 10, 2014Publication date: April 14, 2016Inventors: Srinivas Pulugurtha, Sourabh Dhir, Rajesh N. Gupta, Sanh D. Tang, Si-Woo Lee, Haitao Liu