Abstract: A technique for operating a system including a plurality of processors and a shared resource includes executing a first instruction by a first processor of the plurality of processors. The first instruction generates a reservation of the shared resource for the first processor. The technique includes, after generating the reservation of the shared resource for the first processor, executing a spin lock by the first processor until successful execution of a second instruction acquires a lock of the shared resource. The technique includes disabling interrupts of the first processor in response to an indicator of the successful execution of the second instruction. The first instruction may be a load and reserve instruction and the second instruction may be a conditional store instruction.

Abstract: Aspects of the disclosure relate to barcoded chimeric adeno-associated virus (AAV) capsid libraries, chimeric capsids and related recombinant AAVs (rAAVs) identified using the libraries. Specifically, the chimeric AAV capsid libraries comprise a plurality of nucleic adds encoding AAV capsid proteins, wherein each nucleic acid (i) encodes a unique AAV capsid protein having distinct polypeptide regions of greater than six amino acids in length that are derived from at least two different AAV serotypes, and (ii) comprises a unique barcode sequence. Further disclosed are methods of preparing an AAV library and identifying AAV capsids tropic for a target tissue.

Abstract: The disclosure in some aspects relates to recombinant adeno-associated viruses having distinct tissue targeting capabilities. In some aspects, the disclosure relates to gene transfer methods using the recombinant adeno-associated viruses. In some aspects, the disclosure relates to isolated AAV capsid proteins and isolated nucleic acids encoding the same.

Abstract: Examples include the copy of memory information from a transmit descriptor to a tracking data structure. Some examples include the memory information being copied from a guest transmit descriptor to a tracking data structure of the guest OS and assignment of the guest transmit descriptor back to a free pool, in response to a determination that the guest transmit descriptor is assigned to an intermediate state.

Abstract: The disclosure in some aspects relates to recombinant adeno-associated viruses having distinct tissue targeting capabilities. In some aspects, the disclosure relates to gene transfer methods using the recombinant adeno-associated viruses. In some aspects, the disclosure relates to isolated AAV capsid proteins and isolated nucleic acids encoding the same.

Abstract: The disclosure relates, in some aspects, to compositions and methods for enhanced delivery of a transgene to the central nervous system (CNS) of a subject. In some embodiments, the transgene is delivered by recombinant AAV (rAAV). In some embodiments, the method of enhancing transgene delivery comprises administering a blood brain barrier (BBB)-crossing molecule (e.g., K16ApoE) and an rAAV comprising a transgene to a subject.

Abstract: Aspects of the disclosure relate to barcoded chimeric adeno-associated virus (AAV) capsid libraries, chimeric capsids and related recombinant AAVs (rAAVs) identified using the libraries. Spedfically, the chimeric AAV capsid libraries comprise a plurality of nucleic adds encoding AAV capsid proteins, wherein each nucleic acid (i) encodes a unique AAV capsid protein having distinct polypeptide regions of greater than six amino acids in length that are derived from at least two different AAV serotypes, and (ii) comprises a unique barcode sequence. Further disdosed are methods of preparing an AAV library and identifying AAV capsids tropic for a target tissue.

Abstract: The disclosure in some aspects relates to recombinant adeno-associated viruses having distinct tissue targeting capabilities. In some aspects, the disclosure relates to gene transfer methods using the recombinant adeno-associated viruses. In some aspects, the disclosure relates to isolated AAV capsid proteins and isolated nucleic acids encoding the same.

Abstract: An error-resilient memory device includes sets of memory blocks and redundant memory blocks for storing a set of data bits. A memory block includes a set of memory cells, each memory cell is adjacent to at least two other memory cells, and a memory block is formed by a matrix of the set of memory cells. In a row-folded implementation, a word line is connected to each memory cell, and a set of bit lines is connected to the corresponding set of memory cells. In a column-folded implementation, a bit line is connected to each memory cell, and a set of word lines is connected to the corresponding set of memory cells. A redundant memory block is used to store the set of data bits when the memory block includes a fault.

Abstract: Examples include the copy of memory information from a transmit descriptor to a tracking data structure. Some examples include the memory information being copied from a guest transmit descriptor to a tracking data structure of the guest OS and assignment of the guest transmit descriptor back to a free pool, in response to a determination that the guest transmit descriptor is assigned to an intermediate state.

Abstract: A system for executing an accelerator call function includes a processor, a register context memory, an accelerator scheduler, multiple accelerator cores, and a stack memory. The processor executes a program task. The processor includes a register that stores task context information of the program task. The accelerator call function includes an accelerator operation. The processor forwards the accelerator operation to the accelerator scheduler. Concurrently, the processor stores the task context information in the register context memory. The accelerator scheduler identifies one of the accelerator cores and forwards the accelerator operation to the identified core. The identified core executes the accelerator operation, generates a return value, and stores the return value in the register context memory, which in turn provides the return value and the task context information to the processor.

Abstract: A processor includes a processing unit, a memory, a data cache, an One Block Look-ahead (OBL) prefetch engine, a Stride-Allocate on Miss (AoM) prefetch engine and a prefetch back-off module. The prefetch back-off module assigns and sets a status bits to a prefetched cache line and resets the status bit when the cache line is used by the processing unit. The back-off module also decrements a count value when at least two cache lines are used consecutively by the processing unit, increments the count value when at least two unused cache lines are evicted consecutively from the data cache, and disables cache line prefetching when the count value is greater than zero. The stride-AoM prefetch engine includes a reference pattern table (RPT) that stores details of only those instructions that have undergone a cache miss.

Abstract: A processor includes a processing unit, a memory, a data cache, an One Block Look-ahead (OBL) prefetch engine, a Stride-Allocate on Miss (AoM) prefetch engine and a prefetch back-off module. The prefetch back-off module assigns and sets a status bits to a prefetched cache line and resets the status bit when the cache line is used by the processing unit. The back-off module also decrements a count value when at least two cache lines are used consecutively by the processing unit, increments the count value when at least two unused cache lines are evicted consecutively from the data cache, and disables cache line prefetching when the count value is greater than zero. The stride-AoM prefetch engine includes a reference pattern table (RPT) that stores details of only those instructions that have undergone a cache miss.

Abstract: A method for reducing memory latency in a processor includes identifying an independent instruction (or cache miss instruction) and corresponding dependent instructions from a re-circulating issue window (RIW) when a cache miss is encountered. The cache miss instruction and corresponding dependent instructions are moved to a re-circulating issue buffer (RIB) and moved back to the RIW from the RIB for processing when the cache miss is resolved.

Abstract: A method for reducing memory latency in a processor includes identifying an independent instruction (or cache miss instruction) and corresponding dependent instructions from a re-circulating issue window (RIW) when a cache miss is encountered. The cache miss instruction and corresponding dependent instructions are moved to a re-circulating issue buffer (RIB) and moved back to the RIW from the RIB for processing when the cache miss is resolved.

Abstract: A processor reduces the likelihood of stalls at an instruction pipeline by dynamically extending the size of a full execution queue. To extend the full execution queue, the processor temporarily repurposes another execution queue to store instructions on behalf of the full execution queue. The execution queue to be repurposed can be selected based on a number of factors, including the type of instructions it is generally designated to store, whether it is empty of other instruction types, and the rate of cache hits at the processor. By selecting the repurposed queue based on dynamic factors such as the cache hit rate, the likelihood of stalls at the dispatch stage is reduced for different types of program flows, improving overall efficiency of the processor.

Abstract: A method for estimating energy usage of a program code executed by a very long instruction word (VLIW) processor. The program code includes multiple instructions, which are organized as groups referred to as execution sets. The instructions of an execution set are executed simultaneously. A no operation (NOP) energy and incremental instruction energy for each execution set of the program code are determined to compute a base energy of each execution set. An inter-execution set energy of each execution set is then computed. The estimated energy usage of each execution set is determined by adding the corresponding inter-execution set energies to the base energies. A stall energy consumed on account of executing the program code is then computed. Finally, the estimated energy usage of the program code is determined by adding the stall energy to the determined energies of all the execution sets.

Abstract: A method and system for simultaneously reading data from multiple indexed arrays, where each indexed array includes one or more memory locations and is coupled to a multiplexing circuit. Each multiplexing circuit includes one or more multiplexers and is driven by a set of input selector signals. The method includes enabling each multiplexing circuit with a distinct combination of the set of input selector signals. The distinct combinations of the set of input selector signals cause each input selector signal to drive a comparable number of multiplexers. Each multiplexing circuit selects a memory location from the coupled indexed array. Further, the method includes reading the data at the selected memory locations through the output of each multiplexing circuit.

Abstract: A method and system for simultaneously reading data from multiple indexed arrays, where each indexed array includes one or more memory locations and is coupled to a multiplexing circuit. Each multiplexing circuit includes one or more multiplexers and is driven by a set oft input selector signals. The method includes enabling each multiplexing circuit with a distinct combination of the set of input selector signals. The distinct combinations of the set of input selector signals cause each input selector signal to drive a comparable number of multiplexers. Each multiplexing circuit selects a memory location from the coupled indexed array. Further, the method includes reading the data at the selected memory locations through the output of each multiplexing circuit.

Abstract: A method for estimating energy usage of a program code executed by a very long instruction word (VLIW) processor. The program code includes multiple instructions, which are organized as groups referred to as execution sets. The instructions of an execution set are executed simultaneously. A no operation (NOP) energy and incremental instruction energy for each execution set of the program code are determined to compute a base energy of each execution set. An inter-execution set energy of each execution set is then computed. The estimated energy usage of each execution set is determined by adding the corresponding inter-execution set energies to the base energies. A stall energy consumed on account of executing the program code is then computed. Finally, the estimated energy usage of the program code is determined by adding the stall energy to the determined energies of all the execution sets.