Abstract: Improved fabrication is provided for devices in the GaN material system that require an embedded p-type layer. The effect of Mg diffusion from the p-type layer is compensated for using an GaN interlayer that is etched to be nanoporous at its top surface. In addition to serving as a diffusion barrier, the GaN interlayer preferably has C and O impurities from the etch that tend to compensate unwanted Mg doping in layers above the GaN interlayer. Importantly, the entire structure can be grown at high temperatures, which desirably avoids low temperature growth steps that tend to reduce material quality.

Abstract: In certain examples, methods and semiconductor structures are directed to an integrated circuit (IC) having a diamond layer section and a GaN-based substrate being monolithically integrated or bonded as part of the same IC. In a specific example, the GaN-based substrate includes GaN, AlxGayN (0<x<1; x+y=1) and a dielectric layer, and a diamond layer section which may include polycrystalline diamond. The IC includes: a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, and a diamond-based FET integrated with a portion of the diamond layer section, the diamond FET being electrically coupled to the GaN-based FET and situated over or against a surface region of the GaN-based substrate.

Abstract: In certain examples, methods and semiconductor structures are directed to a method comprising steps of forming by monolithically integrating or seeding via polycrystalline diamond (PCD) particles on a GaN-based layer characterized as including GaN in at least a surface region of the GaN-based layer. After the step of seeding, the PCD particles are grown under a selected pressure to form a diamond layer section and to provide a semi-conductive structure that includes the diamond layer section integrated on or against the surface region of the GaN-based layer.

Abstract: In certain examples, methods and semiconductor structures are directed to use of a doped buried region (e.g., Mg-dopant) including a III-Nitride material and having a diffusion path (“ion diffusion path”) that includes hydrogen introduced by using ion implantation via at least one ion species. An ion implantation thermal treatment causes hydrogen to diffuse through the ion implanted path and causes activation of the buried region. In more specific examples in which such semiconductor structures have an ohmic contact region at which a source of a transistor interfaces with the buried region, the ohmic contact region is without etching-based damage due at least in part to the post-ion implantation thermal treatment.

Abstract: In certain examples, methods and semiconductor structures are directed to an integrated circuit (IC) having a diamond layer section and a GaN-based substrate being monolithically integrated or bonded as part of the same IC. In a specific example, the GaN-based substrate includes GaN, AlxGayN (0<x<1; x+y=1) and a dielectric layer, and a diamond layer section which may include polycrystalline diamond. The IC includes: a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, and a diamond-based FET integrated with a portion of the diamond layer section, the diamond FET being electrically coupled to the GaN-based FET and situated over or against a surface region of the GaN-based substrate.

Abstract: In certain examples, methods and photo-responsive structures are directed to devices involving a diamond-based photoconductive switch having a doped diamond-grown material in the switch. The doped diamond-grown material may be formed from different gases combined on a diamond seed, such that as grown, the diamond-based material manifests a controlled dopant concentration level of a polarity type and over a depth of optical absorption sufficient to ionize the dopants in response to an optical signal.

Abstract: According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

Abstract: Diamond diode-based devices are configured to convert radiation energy into electrical current, useable for sensing (i.e., detection) or delivery to a load (i.e., energy harvesting). A diode-based detector includes an intrinsic diamond layer arranged between p-type diamond and n-type diamond layers, with the detector further including at least one of (i) a boron containing layer arranged proximate to the n-type and/or the intrinsic diamond layers, or (ii) an intrinsic diamond layer thickness in a range of 10 nm to 300 microns. A diode-based detector may be operated in a non-forward biased state, with a circuit used to transmit a current pulse in a forward bias direction to reset a detection state of the detector. An energy harvesting device may include at least one p-i-n stack (including an intrinsic diamond layer between p-type diamond and n-type diamond layers), with a radioisotope source arranged proximate to the at least one p-i-n stack.

Abstract: A semiconductor structure, device, or vertical field effect transistor is comprised of a drain, a drift layer disposed in a first direction relative to the drain and in electronic communication with the drain, a barrier layer disposed in the first direction relative to the drift layer and in electronic communication with the drain, the barrier layer comprising a current blocking layer and an aperture region, a two-dimensional hole gas-containing layer disposed in the first direction relative to the barrier layer, a gate electrode oriented to alter an energy level of the aperture region when a gate voltage is applied to the gate electrode, and a source in ohmic contact with the two-dimensional hole gas-containing layer. At least one of an additional layer, the drain, the drift region, the current blocking layer, the two-dimensional hole gas-containing layer, and the aperture region comprises diamond.

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

Abstract: III-nitride vertical transistors and methods of making the same are disclosed. The transistors can include aperture regions that are formed using ion implantation. The resulting transistors can have improved properties.

Abstract: Apparatuses and methods are provided for manufacturing diamond electronic devices. The method includes at least one of the following acts: positioning a substrate in a plasma enhanced chemical vapor deposition (PECVD) reactor; controlling temperature of the substrate by manipulating microwave power, chamber pressure, and gas flow rates of the PECVD reactor; and growing phosphorus doped diamond layer on the substrate using a pulsed deposition comprising a growth cycle and a cooling cycle.

Abstract: A transistor includes a III-N layer structure including a III-N channel layer between a III-N barrier layer and a III-N depleting layer, where the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer; a source and a drain, each of which being directly connected to the III-N channel layer; a gate between the source and the drain, the gate being over the III-N layer structure, where the III-N depleting layer includes a first portion that is disposed in a device access region between the gate and the drain; and where the source electrically contacts the first portion of the III-N depleting layer, and the drain is electrically isolated from the first portion of the III-N depleting layer.

Abstract: A semiconductor structure, device, or vertical field effect transistor is comprised of a drain, a drift layer disposed in a first direction relative to the drain and in electronic communication with the drain, a barrier layer disposed in the first direction relative to the drift layer and in electronic communication with the drain, the barrier layer comprising a current blocking layer and an aperture region, a two-dimensional hole gas-containing layer disposed in the first direction relative to the barrier layer, a gate electrode oriented to alter an energy level of the aperture region when a gate voltage is applied to the gate electrode, and a source in ohmic contact with the two-dimensional hole gas-containing layer. At least one of an additional layer, the drain, the drift region, the current blocking layer, the two-dimensional hole gas-containing layer, and the aperture region comprises diamond.

Abstract: A transistor includes a III-N layer structure including a III-N channel layer between a III-N barrier layer and a III-N depleting layer, where the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer; a source and a drain, each of which being directly connected to the III-N channel layer; a gate between the source and the drain, the gate being over the III-N layer structure, where the III-N depleting layer includes a first portion that is disposed in a device access region between the gate and the drain; and where the source electrically contacts the first portion of the III-N depleting layer, and the drain is electrically isolated from the first portion of the III-N depleting layer.

Abstract: A semiconductor structure, device, or N-polar III-nitride vertical field effect transistor. The structure, device, or transistor includes a current blocking layer and an aperture region. The current blocking layer and aperture region are comprised of the same material. The current blocking layer and aperture region are formed by polarization engineering and not doping or implantation. A method of making a semiconductor structure, device, or III-nitride vertical transistor. The method includes obtaining, growing, or forming a functional bilayer comprising a barrier layer and a two-dimensional electron gas-containing layer. The functional bilayer is not formed via a regrowth step.

Abstract: A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.

Abstract: Apparatuses and methods are provided for manufacturing diamond electronic devices. The method includes at least one of the following acts: positioning a substrate in a plasma enhanced chemical vapor deposition (PECVD) reactor; controlling temperature of the substrate by manipulating microwave power, chamber pressure, and gas flow rates of the PECVD reactor; and growing phosphorus doped diamond layer on the substrate using a pulsed deposition comprising a growth cycle and a cooling cycle.

Abstract: A semiconductor structure, device, or N-polar Ill-nitride vertical field effect transistor. The structure, device, or transistor includes a current blocking layer and an aperture region. The current blocking layer and aperture region are comprised of the same material The current blocking layer and aperture region are formed by polarization engineering and not doping or implantation. A method of making a semiconductor structure, device, or Ill-nitride vertical transistor. The method includes obtaining, growing, or forming a functional bilayer comprising a barrier layer and a two-dimensional electron gas-containing layer. The functional bilayer is not formed via a regrowth step.

Abstract: According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.