Patents by Inventor Sreenivas Krishnan
Sreenivas Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240168903Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.Type: ApplicationFiled: January 26, 2024Publication date: May 23, 2024Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
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Patent number: 11907150Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.Type: GrantFiled: May 10, 2021Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
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Publication number: 20210263871Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
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Patent number: 11003609Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.Type: GrantFiled: August 14, 2020Date of Patent: May 11, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
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Patent number: 10929325Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.Type: GrantFiled: January 9, 2020Date of Patent: February 23, 2021Assignee: INPHI CORPORATIONInventors: Sreenivas Krishnan, Nirmal Raj Saxena
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Publication number: 20200379933Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.Type: ApplicationFiled: August 14, 2020Publication date: December 3, 2020Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
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Patent number: 10776299Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.Type: GrantFiled: June 6, 2019Date of Patent: September 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
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Patent number: 10649667Abstract: A system and method for managing garbage collection in Solid State Drives (SSDs) in a Redundant Array of Independent Disks (RAID) configuration, using a RAID controller is described. A control logic can control read and write requests for the SSDs in the RAID configuration. A selection logic can select an SSD for garbage collection. Setup logic can instruct the selected SSD to enter a garbage collection setup phase. An execute logic can instruct the selected SSD to enter and exit the garbage collection execute phase.Type: GrantFiled: September 22, 2017Date of Patent: May 12, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Oscar Pinto, Sreenivas Krishnan
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Publication number: 20200142852Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.Type: ApplicationFiled: January 9, 2020Publication date: May 7, 2020Inventors: Sreenivas KRISHNAN, Nirmal Raj SAXENA
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Patent number: 10572425Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.Type: GrantFiled: February 5, 2019Date of Patent: February 25, 2020Assignee: INPHI CORPORATIONInventors: Sreenivas Krishnan, Nirmal Raj Saxena
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Publication number: 20190286595Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard.Type: ApplicationFiled: June 6, 2019Publication date: September 19, 2019Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
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Patent number: 10360166Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.Type: GrantFiled: June 29, 2018Date of Patent: July 23, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
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Publication number: 20190171605Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.Type: ApplicationFiled: February 5, 2019Publication date: June 6, 2019Inventors: Sreenivas KRISHNAN, Nirmal Raj SAXENA
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Patent number: 10235318Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.Type: GrantFiled: November 14, 2017Date of Patent: March 19, 2019Assignee: INPHI CORPORATIONInventors: Sreenivas Krishnan, Nirmal Raj Saxena
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Publication number: 20180329844Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.Type: ApplicationFiled: June 29, 2018Publication date: November 15, 2018Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
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Patent number: 10114778Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.Type: GrantFiled: April 4, 2016Date of Patent: October 30, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
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Patent number: 10002586Abstract: Display data used in display frame generation are compressed for efficient storage in a local memory within a graphics processing unit. The compression technique used is difference encoding and before performing difference encoding, display data in RGB format are converted into YCbCr format. Since the component values of adjacent pixels in YCbCr format typically vary less than the component values of the same adjacent pixels in RGB format, converting the display data to YCbCr format before performing difference encoding improves the compression efficiency.Type: GrantFiled: December 13, 2006Date of Patent: June 19, 2018Assignee: NVIDIA CORPORATIONInventors: Sreenivas Krishnan, Koen Bennebroek, Karthik Bhat, Stefano A. Pescador, David G. Reed, Brad W. Simeral, Edward M. Veeser
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Publication number: 20180067887Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.Type: ApplicationFiled: November 14, 2017Publication date: March 8, 2018Inventors: Sreenivas KRISHNAN, Nirmal Raj SAXENA
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Publication number: 20180011641Abstract: A system and method for managing garbage collection in Solid State Drives (SSDs) in a Redundant Array of Independent Disks (RAID) configuration, using a RAID controller is described. A control logic can control read and write requests for the SSDs in the RAID configuration. A selection logic can select an SSD for garbage collection. Setup logic can instruct the selected SSD to enter a garbage collection setup phase. An execute logic can instruct the selected SSD to enter and exit the garbage collection execute phase.Type: ApplicationFiled: September 22, 2017Publication date: January 11, 2018Inventors: Oscar PINTO, Sreenivas KRISHNAN
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Patent number: 9846669Abstract: A computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and can include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. The plurality of rack modules can each include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.Type: GrantFiled: July 29, 2016Date of Patent: December 19, 2017Assignee: INPHI CORPORATIONInventors: Sreenivas Krishnan, Nirmal Raj Saxena