Abstract: A system and method for managing garbage collection in Solid State Drives (SSDs) (120-1, 120-2, 120-3, 120-4, 120-5) in a Redundant Array of Independent Disks (RAID) configuration, using a RAID controller (115) is described. A control logic (505) can control read and write requests (805, 810) for the SSDs (120-1, 120-2, 120-3, 120-4, 120-5) in the RAID configuration. A selection logic (515) can select an SSD for garbage collection. Setup logic (520) can instruct the selected SSD to enter a garbage collection setup phase (920). An execute logic (525) can instruct the selected SSD to enter and exit the garbage collection execute phase (925).

Abstract: A computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and can include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. The plurality of rack modules can each include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.

Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.

Abstract: A computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and can include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. The plurality of rack modules can each include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.

Abstract: Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.

Abstract: Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.

Abstract: A memory access pipeline within a subsystem is configured to manage memory access requests that are issued by clients of the subsystem. The memory access pipeline is capable of providing a software baseband controller client with sufficient memory bandwidth to initiate and maintain network connections. The memory access pipeline includes a tiered snap arbiter that prioritizes memory access requests. The memory access pipeline also includes a digital differential analyzer that monitors the amount of bandwidth consumed by each client and causes the tiered snap arbiter to buffer memory access requests associated with clients consuming excessive bandwidth. The memory access pipeline also includes a transaction store and latency analyzer configured to buffer pages associated with the baseband controller and to expedite memory access requests issued by the baseband controller when the latency associated with those requests exceeds a pre-set value.

Abstract: A memory controller provided according to an aspect of the present invention includes a predictor block which predicts future read requests after converting the memory address in a prior read request received from the processor to an address space consistent with the implementation of a memory unit. According to another aspect of the present invention, the predicted requests are granted access to a memory unit only when there are no requests pending from processors and the peripherals sending access requests to the memory unit.

Abstract: A method includes operating an arbitration logic of a memory controller at a core clock frequency lower than that of a memory clock frequency. The memory controller is configured to generate a command sequence including a number of commands in accordance with a number of external requests to access the memory. The method also includes parallelizing the number of commands in the command sequence based on a timing requirement for a non-first command in the command sequence defined by a memory-access protocol being satisfied at a rising edge or a falling edge of the core clock relative to a previous command in the command sequence. Further, the method includes ensuring, through the parallelizing, availability of the number of commands in the command sequence to a memory interface operating at the memory clock frequency at a command rate equal to the memory clock frequency.

Abstract: A method includes operating an arbitration logic of a memory controller at a core clock frequency lower than that of a memory clock frequency. The memory controller is configured to generate a command sequence including a number of commands in accordance with a number of external requests to access the memory. The method also includes parallelizing the number of commands in the command sequence based on a timing requirement for a non-first command in the command sequence defined by a memory-access protocol being satisfied at a rising edge or a falling edge of the core clock relative to a previous command in the command sequence. Further, the method includes ensuring, through the parallelizing, availability of the number of commands in the command sequence to a memory interface operating at the memory clock frequency at a command rate equal to the memory clock frequency.

Abstract: A memory controller provided according to an aspect of the present invention includes a predictor block which predicts future read requests after converting the memory address in a prior read request received from the processor to an address space consistent with the implementation of a memory unit. According to another aspect of the present invention, the predicted requests are granted access to a memory unit only when there are no requests pending from processors and the peripherals sending access requests to the memory unit.