Patents by Inventor Sridhar Srinivasan

Sridhar Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10834191
    Abstract: In various embodiments, methods and systems for enhanced access to storage data based on a collaboration data proxy system are provided. A plurality of metadata tables on one or more peer nodes are referenced for data corresponding to a data request of a requesting node. The metadata tables indicate availability of chunks of data in the one or more peer nodes. A determination is made that the data corresponding to the data request is downloadable from the one or more node; the determination is based on the metadata tables. A download operation configuration instance is generated for a data request of a requesting node. The download operation configuration instance comprises configuration settings for downloading data corresponding to the data request from the one or more peer nodes. The chunk of data is downloaded from the corresponding one or more peer nodes where the chunk is located, using the configuration settings.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: November 10, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nicolaas Deodorus Peelen, Wang Hui, Jun Tang, Sridhar Srinivasan, Mingqiang Xu, Yan Huang
  • Patent number: 10805616
    Abstract: Techniques and tools for performing fading compensation in video processing applications are described. For example, during encoding, a video encoder performs fading compensation using fading parameters comprising a scaling parameter and a shifting parameter on one or more reference images. During decoding, a video decoder performs corresponding fading compensation on the one or more reference images.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Shankar Regunathan
  • Patent number: 10796045
    Abstract: Systems and methods for efficient bi-directional property-based path tracing. The method includes reading a data structure corresponding to a circuit. The method also includes iteratively performing property accounting of properties as voltages propagate across devices in the circuit. The method also includes traversing series chains of similar devices in the circuit to reduce an iteration count and arrive at a circuit stability, wherein the circuit stability is determined when propagated user-specified and computed circuit properties (e.g. shortest distance) remain unchanged between subsequent iterations of the traversing. The method also includes traversing the data structure for propagated user-specified and computed property violations. The method also includes cataloging and reporting these violations in human-readable form.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: October 6, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Mark E. Hofmann, Sridhar Srinivasan
  • Patent number: 10769340
    Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: September 8, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Sridhar Srinivasan, Yi-Ting Lee, Patrick D. Gibson, Padmaja Susarla, Alex Thompson
  • Publication number: 20200221091
    Abstract: A digital media encoder/decoder uses a flexible quantization technique that provides the ability to vary quantization along various dimensions of the encoded digital media data, including spatial, frequency sub bands and color channels. The codec utilizes a signaling scheme to signal various permutations of flexible quantization combinations efficiently for primary usage scenarios. When a choice of quantizer is available, the codec efficiently encodes the current quantizer by defining a subset of quantizers and indexes the current quantizer from the set.
    Type: Application
    Filed: March 20, 2020
    Publication date: July 9, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Chengjie Tu, Sridhar Srinivasan
  • Publication number: 20200177893
    Abstract: Techniques and tools are described for decoding jointly coded information. For example, a decoder decodes a variable length code [“VLC”] signaled at macroblock level that jointly represents a transform type signal level, transform type, and subblock pattern. The decoder decodes one or more VLCs signaled at block level, each jointly representing a transform type and subblock pattern. The decoder may select between multiple VLC tables for the VLCs signaled macroblock level and/or block level.
    Type: Application
    Filed: February 4, 2020
    Publication date: June 4, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Chih-Lung Lin, Shankar Regunathan, Sridhar Srinivasan
  • Publication number: 20200177892
    Abstract: A video codec uses fractional increments of quantization step size at high bit rates to permit a more continuous variation of quality and/or bit rate as the quantization scale changes. For high bit rate scenarios, the bit stream syntax includes an additional syntax element to specify fractional step increments (e.g., half step) of the normal quantizer scale step sizes.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Sridhar Srinivasan, Pohsiang Hsu, Chih-Lung Lin
  • Publication number: 20200177890
    Abstract: Described tools and techniques relate to signaling for DC coefficients at small quantization step sizes. The techniques and tools can be used in combination or independently. For example, a tool such as a video encoder or decoder processes a VLC that indicates a DC differential for a DC coefficient, a FLC that indicates a value refinement for the DC differential, and a third code that indicates the sign for the DC differential. Even with the small quantization step sizes, the tool uses a VLC table with DC differentials for DC coefficients above the small quantization step sizes. The FLCs for DC differentials have lengths that vary depending on quantization step size.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Chih-Lung Lin, Shankar Regunathan, Sridhar Srinivasan
  • Publication number: 20200177891
    Abstract: With adaptive multiple quantization, a video or other digital media codec can adaptively select among multiple quantizers to apply to transform coefficients. The switch in quantizers can be signaled at the sequence level or frame level of the bitstream syntax, or can be implicitly specified in the syntax.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Sridhar Srinivasan
  • Publication number: 20200169749
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Patent number: 10659793
    Abstract: Described tools and techniques relate to signaling for DC coefficients at small quantization step sizes. The techniques and tools can be used in combination or independently. For example, a tool such as a video encoder or decoder processes a VLC that indicates a DC differential for a DC coefficient, a FLC that indicates a value refinement for the DC differential, and a third code that indicates the sign for the DC differential. Even with the small quantization step sizes, the tool uses a VLC table with DC differentials for DC coefficients above the small quantization step sizes. The FLCs for DC differentials have lengths that vary depending on quantization step size.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chih-Lung Lin, Shankar Regunathan, Sridhar Srinivasan
  • Publication number: 20200142878
    Abstract: A distributed storage system includes non-volatile storage storing portions of a first object. The first object encompasses data having a first range of addresses and each portion includes data for a respective range of addresses that is a proper subset of the first range. A first data structure stores, for each portion, data indicating the respective range of addresses and a pointer to where the portion is stored. The first data structure includes a root tree and a set of trees ordered by creation data such that a last tree is most-recently created. The non-volatile storage stores received write data and a write buffer stores index data pointing to storage locations of the received write data. An index management system stores the index data from the write buffer into the last tree and, if the ordered set is empty, creates a tree in the ordered set before the storing.
    Type: Application
    Filed: June 30, 2017
    Publication date: May 7, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Krishnan VARADARAJAN, Jegan DEVARAJU, Shane MAINALI, Quan ZHANG, Sridhar SRINIVASAN, Bin TONG, He SU, Ju WANG, Manish CHABLANI, Hao FENG
  • Patent number: 10642249
    Abstract: A method for real-time damage prediction includes obtaining a damage prediction model that mathematically models expected damage to equipment in an industrial process based on a plurality of process parameters. The method also includes obtaining real-time state information for at least one of the plurality of process parameters. The method further includes determining, based on the real-time state information and the damage prediction model, a real-time prediction of damage to at least one component of the equipment in the industrial process. The method may also include obtaining historical data for the plurality of process parameters, and the real-time prediction of damage can be based on the historical data, the real-time state information, and the damage prediction model. The method may further include identifying and adjusting a high limit and a low limit for the at least one of the plurality of process parameters.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 5, 2020
    Assignee: Honeywell International Inc.
    Inventor: Sridhar Srinivasan
  • Patent number: 10616318
    Abstract: A system includes a load balancer and storage including a first data structure and a second data structure. Each of the data structures includes a plurality of different weight levels. At least one of the weight levels of the first data structure includes an identifier of a target. At least one of the weight levels of the second data structure includes a map that associates a target identifier with a final weight value. Responsive to receipt of a request and responsive to a target identifier included at a given weight level in the first data structure corresponding to a pointer, the load balancer selects the target identified in the first data structure at the given weight level. Responsive to no target identifiers included at the given weight level in the first data structure, the load balancer selects a target identified in the second data structure at the given weight level. The load balancer forwards the request to the selected target.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Anurag Sanjay Katey, Sridhar Srinivasan, Hamza Muhammad Arain
  • Patent number: 10596219
    Abstract: A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: March 24, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Sridhar Srinivasan, Fedor G. Pikus, Patrick D. Gibson, Padmaja Susarla
  • Patent number: 10602146
    Abstract: A digital media encoder/decoder uses a flexible quantization technique that provides the ability to vary quantization along various dimensions of the encoded digital media data, including spatial, frequency sub bands and color channels. The codec utilizes a signaling scheme to signal various permutations of flexible quantization combinations efficiently for primary usage scenarios. When a choice of quantizer is available, the codec efficiently encodes the current quantizer by defining a subset of quantizers and indexes the current quantizer from the set.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 24, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chengjie Tu, Sridhar Srinivasan
  • Patent number: 10592628
    Abstract: Aspects of the disclosed technology relate to techniques of parasitic extraction using compact representation of process calibration data. Geometric information of a layout feature in the layout design comprising geometric parameters is extracted. Parasitic values associated with the layout feature are then computed based on the geometric information and one or more executable files selected in a plurality of executable files which are a compact representation of process calibration data.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 17, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Sandeep Koranne, Sridhar Srinivasan
  • Patent number: 10567753
    Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: February 18, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Pohsiang Hsu
  • Patent number: 10567791
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 18, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Patent number: 10554985
    Abstract: Described tools and techniques relate to signaling for DC coefficients at small quantization step sizes. The techniques and tools can be used in combination or independently. For example, a tool such as a video encoder or decoder processes a VLC that indicates a DC differential for a DC coefficient, a FLC that indicates a value refinement for the DC differential, and a third code that indicates the sign for the DC differential. Even with the small quantization step sizes, the tool uses a VLC table with DC differentials for DC coefficients above the small quantization step sizes. The FLCs for DC differentials have lengths that vary depending on quantization step size.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 4, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chih-Lung Lin, Shankar Regunathan, Sridhar Srinivasan