Abstract: The present disclosure relates to a method including providing a die including a cavity therein, wherein the die further may include a die fiducial on a top surface. The method further includes placing a lens structure in the cavity of the die, wherein the lens structure may include a lens fiducial on a front surface. The method also includes moving the lens structure in the cavity to a position until a lens fiducial image may be captured in an image processing system when the lens fiducial and the die fiducial coincide and lie in a plane orthogonal to the top surface of the die. A corresponding system is also disclosed herein.

Abstract: An interconnect that has an electrically conductive layer, where a first and second insulator layers are coupled with the conductive layer. A region of the conductive layer includes an opening of a portion of the first insulator layer the second insulator layer that are adjacent to the region. An electrical connector of a first device is electrically coupled to a portion of the region on a first side of the conductive layer and an electrical conductor of a second device is electrically coupled with a portion of the region on the second side. Also, an interconnect coupled with a substrate that includes a cylinder extending from a side of the substrate with a plate coupled at the end of the cylinder with an opening that includes two or more tabs of the plate extending into the opening to receive a connector.

Abstract: Techniques and mechanisms for coupling packaged devices with a dual-sided socket device. In an embodiment, two interfaces of the socket device comprise, respectively, first metallization structures and second metallization structures on opposite sides of a socket body structure. The first metallization structures each form a respective corrugation structure to electrically couple with a corresponding conductive contact of a first packaged device. The corrugation structures facilitate such electrical coupling each via a vertical wipe of the corresponding conductive contact. In another embodiment, a pitch of the first metallization structures is in a range of between 0.1 millimeters (mm) and 2 mm. One such metallization structure has a vertical span in a range of between 0.05 mm and 2.0 mm, where a portion of a side of the metallization structure forms a corrugation structure, and has a horizontal span which is at least 5% of the vertical span.

Abstract: In one embodiment, an integrated circuit assembly includes a substrate comprising electrical connectors on a top side of the substrate and an integrated circuit die coupled to the top side of the substrate. The integrated circuit die includes metal pillars extending from a bottom side of the die facing the top side of the substrate, and the metal pillars of the integrated circuit die are electrically connected to the electrical connectors of the substrate via a liquid metal (e.g., a Gallium-based alloy).

Abstract: Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.

Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonics engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.

Abstract: The present disclosure relates to a method including providing a die including a cavity therein, wherein the die further may include a die fiducial on a top surface. The method further includes placing a lens structure in the cavity of the die, wherein the lens structure may include a lens fiducial on a front surface. The method also includes moving the lens structure in the cavity to a position until a lens fiducial image may be captured in an image processing system when the lens fiducial and the die fiducial coincide and lie in a plane orthogonal to the top surface of the die. A corresponding system is also disclosed herein.

Abstract: A microelectronic structure, a semiconductor package including the same, and a method of forming same. The microelectronic structures includes: a substrate defining a cavity therein; a bridge die within the cavity, the bridge die to electrically couple a pair of dies to be provided on a surface of the substrate; an electrical coupling layer between a top surface of the cavity and a bottom surface of the bridge die. The electrical coupling layer includes: a non-conductive component including a die bonding film and defining holes therein; and electrically conductive structures in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die.

Abstract: A receptacle of a photonics package, a receptacle assembly including the receptacle, the photonics package, and a method of making the receptacle assembly. The receptacle assembly comprises: a photonics integrated circuit (PIC) including waveguides thereon; a die side lens assembly; and a rigid receptacle body including: a plug portion to receive an optical plug that includes a plug side lens assembly; a lens portion supporting the die side lens assembly and configured such that the die side lens assembly and the plug side lens assembly are aligned to one another when the optical plug is received in the plug portion; and a PIC portion bonded to the PIC such that the waveguides of the PIC are aligned to: corresponding lenses of the die side lens assembly; and corresponding lenses of the plug side lens assembly when the optical plug is received in the plug portion.

Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.

Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes a processor package including at least one processor integrated circuit (IC); an interposer including electrically conductive interposer interconnect; a first liquid metal well array including multiple liquid metal wells arranged between the processor package and the interposer, wherein the first liquid metal well array is attached to a surface of the processor package and attached to a first surface of the interposer and the interposer interconnect; a printed circuit board (PCB) attached to a second surface of the interposer and the interposer interconnect; a second liquid metal well array including a first surface attached to the first surface of the interposer and the interposer interconnect; and a first companion component package attached to a second surface of the second liquid metal well array.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an integrated circuit (IC) package substrate including package interconnect and a first substrate surface; a processor IC attached to the first substrate surface and electrically connected to the package interconnect; a liquid metal well array including multiple liquid metal wells, a first array surface attached to the first substrate surface, and a second array surface; and a companion component to the processor IC attached to the second array surface of the liquid metal well array.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a socket that includes one or more liquid metal filled reservoirs. In selected examples, the electronic devices and sockets include configurations to aid in reducing ingress of moisture.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes liquid metal pathways that form one or more conduction pathway through one or more dielectric layers. In selected examples, the dielectric layers are resilient, which allows for flexibility of interconnect components.

Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In the illustrative embodiment, a lens assembly with one or more lenses is positioned to collimate light coming out of one or more waveguides in the PIC die. Part of the illustrative lens assembly extends above a top surface of the PIC die and is in contact with the PIC die. The top surface of the PIC die establishes the vertical positioning of the lens assembly. In the illustrative embodiment, the lens assembly is positioned at least partially inside a cavity defined within the PIC die, which allows the lens assembly to be integrated at the wafer level, before singulation into individual dies.

Abstract: An electronic device comprises a photonic integrated circuit (PIC) including at least one optical signal source, an emitting lens disposed on the PIC to steer light emitted by the at least one optical signal source in a direction substantially parallel to a first surface of the PIC, and an optical element disposed on the PIC and having a curved surface in a shape of a quarter cylinder that is configured to steer light emitted from the emitting lens in a direction substantially orthogonal to the first surface of the PIC.

Abstract: Technologies for applying gold-plated contact pads to circuit boards are disclosed. In one embodiment, an array of gold-plated contact pads is prepared on a flexible substrate. The array of gold-plated contact pads can then be transferred to a circuit board, such as by soldering the gold-plated contact pads to the circuit board. In another embodiment, an array of contact pads are prepared on a top and bottom surface of a substrate, and vias are added to connect the contact pads on the top and bottom surfaces. The top array of contact pads are gold-plated. The bottom array of contact pads are mated to a circuit board. Techniques described herein allow for gold-plated contact pads to be applied to a circuit board without requiring the entire circuit board to undergo a gold plating process, which may reduce manufacturing costs.

Abstract: Systems, apparatus, and/or processes directed to applying pressure to a socket to alter a shape of the socket to improve a connection between the socket and a substrate, printed circuit board, or other component. The socket may receive one or more chips, may be an interconnect, or may be some other structure that is part of a package. The shape of the socket may be flattened so that a side of the socket may form a high-quality physical and electrical coupling with the substrate.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a cavity created in a package substrate, where the surface of the substrate at the bottom of the cavity, or alignment features at the surface of the substrate at the bottom of the cavity are used to accurately align a lens of a FAU to a lens of a PIC. In embodiments, the surface of the substrate at the bottom of the cavity has additional standoff pedestal features to aid in height tolerance control of the FAU to properly align the FAU lens when attached. Other embodiments may be described and/or claimed.

Abstract: Techniques and mechanisms for facilitating horizontal communication with a photonic integrated circuit (PIC) chip, and a lens structure which is optically coupled thereto. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective first divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A lens structure, which is adjacent to the IECs, comprises a second divergent lens surface having an orientation which is substantially orthogonal to the respective orientations of the first divergent lens surfaces. In another embodiment, an edge of the PIC chip forms one or more recess structures, and the lens structure comprises one or more tenon portions which each extends into a respective recess structure of the one or more recess structures.